TV-PUF: A Fast Lightweight Analog Physical Unclonable Function (original) (raw)
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An efficient reliable PUF-based cryptographic key generator in 65nm CMOS
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, 2014
Physical unclonable functions (PUFs) are primitives that generate high-entropy, tamper resistant bits for use in secure systems. For applications such as cryptographic key generation, the PUF response bits must be highly reliable, consistent across multiple evaluations under voltage and temperature variations. Conventionally, error correcting codes (ECC) have been used to improve response reliability, but these techniques have significant area, power, and delay overheads and are vulnerable to information leakage. In this work, we present a highly-reliable, PUF-based, cryptographic key generator that uses no ECC, but instead uses built-in self-test to determine which PUF bits are reliable and only uses those bits for key generation. We implemented a prototype of the key generator in a 65nm bulk CMOS testchip. The key generator generates 1213 bits in an area of <50kµm 2 with a measured bit error rate of < 5 * 10 −9 in both the nominal and worst case corners (100k measurements each). This is equivalent to a 128-bit key failure rate of < 10 −6. The system can generate a 128-bit key in 1.15µs. Finally, we present a realization of a "strong"-PUF that uses 128 of these highly reliable bits in conjunction with an Advanced Encryption Standard (AES) cryptographic primitive and has a response time of 40ns and is realized in an area of 84kµm 2 .
Embedded Analog Physical Unclonable Function System to Extract Reliable and Unique Security Keys
Applied Sciences
Internet of Things (IoT) enabled devices have become more and more pervasive in our everyday lives. Examples include wearables transmitting and processing personal data and smart labels interacting with customers. Due to the sensitive data involved, these devices need to be protected against attackers. In this context, hardware-based security primitives such as Physical Unclonable Functions (PUFs) provide a powerful solution to secure interconnected devices. The main benefit of PUFs, in combination with traditional cryptographic methods, is that security keys are derived from the random intrinsic variations of the underlying core circuit. In this work, we present a holistic analog-based PUF evaluation platform, enabling direct access to a scalable design that can be customized to fit the application requirements in terms of the number of required keys and bit width. The proposed platform covers the full software and hardware implementations and allows for tracing the PUF response ge...
Innovative Systems Design and Engineering, 2017
Physical Un-clonable Function (PUF) is a physical entity that provides secret key or fingerprints in silicon circuits by exploiting the uncontrollable randomness during its manufacturing randomness. It provides a hardware unique signature or identification. Its property of uniqueness comes from its unpredictable way of mapping challenges to responses, even if it was manufactured with the same process. Previous work has mainly focused on novel structures for non-FPGA reconfigurable silicon PUFs which does not need any special fabrication method and which can overcome the limitations of FPGA-based simulations. Their performance was quantified by the inter-chip variations, intra-chip variations and re-configurability tests to meet practical application needs. This paper presents a novel approach of designing a low power non-FPGA feed-forward PUF using double gate MOSFET and also to analyze its parameters such as intra-chip variation, reliability and power. Keywords: Physical Un-clon...
TV-PUF : A Fast Lightweight Aging-Resistant Threshold Voltage PUF
2016
Physical Unclonable Function (PUF) is the hardware analog of a one-way function which can address hardware security issues such as device authentication, generating secret keys, producing seeds for Random Number Generators, etc. Traditional silicon PUFs are based on delay (Ring Oscillator PUFs and Arbiter PUFs) or memory structures (e.g, SRAM PUFs). In this paper, we propose the design of an aging resistant, lightweight and low-power analog PUF that exploits the susceptibility of Threshold Voltage (Vth) of MOSFETs to process variations. Analysis shows improvement in power consumption, reliability over device aging along with quality metrics like uniformity, reliability and uniqueness for a 64-bit key generation. For 1 GHz clock input, this design consumes 0.18μW/bit power with 50 % uniqueness and 51% uniformity along with the independence of these metrics on technology nodes. Experimental results suggest 4% variation in reliability under temperature variation from -55◦C to 125◦C and...
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018
Strong physical unclonable function (PUF) transcends the limitations of legacy secure key storage methods as emerging security primitive for cryptography and device identification/authentication. In this paper, a new low power and reliable mono-stable strong PUF is proposed. Its primary entropy is derived from the process variations of the parallel diode-clamped single inverter ring working in the subthreshold region. Due to manufacturing process variations, the monostable state of the output voltage of single inverter ring is Gaussian distributed around the half V dd point. The spread of the Gaussian is broadened by mixing it with another Gaussian distributed trip point obtained from a diode-clamped parallel inverter stage. As the main entropy of the raw response bits is derived from a mono-stable circuit, it has greater immunity to perturbances introduced by operating environments. In addition, as the mono-stable state for the output voltage is a non-linear combination of individual inverter rings, the resilience against machine learning attacks can be improved. The prototype chip was fabricated using a commercial 40-nm CMOS technology. The measurement results show that the power consumption of the 64-bit mono-stable PUF is merely 3.85 µW. The native bit error rate is <8% at 0.9 ∼ 1.3 V and −40∼ 90 • C, which can be further reduced to <1% using the proposed thresholding technique. The proposed PUF reduces the accuracy of support vector machine and reliability-based covariance matrix adaptation evolution strategy attacks by 36× and 75×, respectively, over that of arbiter PUF.
IEEE Access, 2019
As burgeoning hardware security primitive, physical unclonable function (PUF) has aroused the interest of solid-state circuit community on its efficient integration into security-critical applications. This paper presents an energy efficient implementation of classic arbiter PUF design. Current-starved (CS) inverters are inserted at the inputs of each multiplexer cell to reduce the skew and widen the distribution of the delay difference between two symmetric daisy-chained delay paths selectable by the input challenge. The CS-inverters are biased at the zero temperature coefficient (ZTC) point, making the accumulated delays of the two identical paths insensitive to temperature variations. A symmetric two RS latches based arbiter is proposed to overcome the asymmetric input and clock to the output propagation delay of D flip-flop and the metastability problem of RS latch arbiter. By limiting the drain currents of CS-inverters to achieve ZTC, the power consumption of the proposed PUF is also reduced substantially. The performance of the proposed PUF design has been successfully validated by the responses measured from prototype chips fabricated in standard 65 nm CMOS process. The fabricated chips feature a compact silicon area of 3838 µm 2 and low energy consumption of 2.74 pJ per bit at 25 Mbps, with measured uniqueness of 46.8% and native bit error rate (BER) of 0.8%. It is worst-case BER is less than 10.46% measured over an extended ∼7x temperature range and ∼5x supply voltage range. These physically measured figures of merit have outperformed previously reported measurements of strong PUFs with similar linear additive delay architecture. INDEX TERMS Strong physical unclonable function, lightweight authentication, low power consumption, current-starved inverter.
Reliability and security of arbiter-based physical unclonable function circuits
International Journal of Communication Systems, 2012
Physical unclonable functions (PUFs) are considered as a promising technology that would be used for secure key generation and storage, integrated circuit (IC) authentication, and chip-unique signature generation. On the basis of the delay variation of logic gates across ICs, PUF circuits could be used to generate secret keys attached to some challenge-response schemes. In this study, an arbiter-based PUF circuit is implemented on Xilinx Virtex 2 Pro field-programmable gate array (Xilinx, Inc., San Jose, CA, USA), and its identification capability, reliability, and security are investigated. For this purpose, we define and measure the parameters such as interchip variation and environmental noise, which are important in the identification process of different ICs. In order to test the resistance of PUF circuit against software attacks, we applied two approaches. In the first one, we use a support vector machine classifier, and attacks are considered as a classification problem. In the second one, linear programming technique is applied to find the delay variables corresponding to the linear model of the PUF circuit.
DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices
2021
In recent years, physical unclonable functions (PUFs) have gained a lot of attention as mechanisms for hardware-rooted device authentication. While the majority of the previously proposed PUFs derive entropy using dedicated circuitry, software PUFs achieve this from existing circuitry in a system. Such software-derived designs are highly desirable for low-power embedded systems as they require no hardware overhead. However, these software PUFs induce considerable processing overheads that hinder their adoption in resource-constrained devices. In this article, we propose DTA-PUF, a novel, software PUF design that exploits the instruction- and data-dependent dynamic timing behaviour of pipelined cores to provide a reliable challenge-response mechanism without requiring any extra hardware. DTA-PUF accepts sequences of instructions as an input challenge and produces an output response based on the manifested timing errors under specific over-clocked settings. To lower the required proce...
A secure arbiter physical unclonable functions (PUFs) for device authentication and identification
Indonesian Journal of Electrical Engineering and Informatics (IJEEI)
Recent fourth industrial revolution, industry4.0 results in lot of automation of industrial processes and brings intelligence in many home appliances in the form of IoT, enhances M2M / D2D communication where electronic devices play a prominent role. It is very much necessary to ensure security of those devices. To provide reliable authentication and identification of each device and to abort the counterfeiting from the unauthorized foundries Physical Unclonable Functions (PUFs) emerged as a one of the promising cryptographic hardware security solution. PUF is function, mathematically modeled by using uncontrollable/ unavoidable random variances of the fabrication process of the ICs. These variances can generate unpredictable, random responses can be used to overcome the difficulties such as storing the keys in non-volatile memories (NVMs) in the classical cryptography. A wide variety of PUF architectures such as Arbiter PUFs, Ring oscillator PUFs, SRAM PUFs proposed by authors. But due to its design complexity and low cost, Delay based Arbiter PUFs (D-PUFs) are considering to be a one of the security primitives in authentication applications such as low-cost IoT devices for secure key generation. This paper presents a review on the different types of Delay based PUF architectures proposed by the various authors, sources to exhibit the physical disorders in ICs, methods to estimate the Performance metrics and applications of PUF in different domains.
Physical Unclonable Functions (PUF) for IoT Devices
ACM Computing Surveys
Physical Unclonable Function (PUF) has recently attracted interest from both industry and academia as a potential alternative approach to secure Internet of Things (IoT) devices from the more traditional computational-based approach using conventional cryptography. PUF is a promising solution for lightweight security, where the manufacturing fluctuation process of IC is used to improve the security of IoT as it provides low complexity design and preserves secrecy. PUF provides a low-cost low-power solution and can be implemented in both Field Programmable Gate Arrays (FPGA) and Application-Specific Integrated Circuits (ASICs). In this survey, we provide a comprehensive review of the state-of-the-art of PUF, its architectures, protocols and security for IoT.