Technologies for 3D wafer level heterogeneous integration (original) (raw)

Through silicon via technology — processes and reliability for wafer-level 3D system integration

2008 58th Electronic Components and Technology Conference, 2008

3D integration is a rapidly growing topic in the semiconductor industry that encompasses different types of technologies. The paper addresses one of the most promising technologies which uses through silicon vias (TSV) for interconnecting stacked devices on wafer-level to perform high density interconnects with a good electrical performance at the smallest form factor for 3D architectures. Fraunhofer IZM developed a post frontend 3D integration process, the socalled ICV-SLID technology based on metal bonding using solid-liquid-interdiffusion (SLID) soldering. The SLID metal system provides the mechanical and the electrical connection, both in one single step. The ICV-SLID fabrication process is well suited for the cost-effective production of both, highperformance applications (e.g. 3D microprocessor) and highly miniaturized multi-functional systems. The latter preferably in combination with wafer-level die stacking, as e.g. Thin Chip Integration (TCI) or SnAg-microbump technologies. The fabrication of distributed wireless sensor systems (e. g. e-CUBES®) is a typical example for the need of such mixed approaches.

3D silicon integration

2008

Three-dimensional (3D) chip integration may provide a path to miniaturization, high bandwidth, low power, high performance and system scaling. Integration options can leverage stacked die and/or silicon packages depending on applications. The enabling technology elements include: (i) through-silicon-vias (TSV) with thinned silicon wafers, (ii) fine pitch wiring, (iii) fine pitch interconnection between stacked die, (iv) fine pitch test for known-good die, and (v) power delivery, distribution and thermal cooling technology. Applications may range from miniaturization of portable electronics like image sensors and cell phones to power efficient, high performance computing solutions such as servers and super computers.

CMOS-Compatible Through Silicon Vias for 3D Process Integration

MRS Proceedings, 2006

ABSTRACTAs the limits of traditional CMOS scaling are approached, process integration has become increasingly difficult and resulting in a diminished rate of performance improvement over time. Consequently, the search for new two- and three- dimensional sub-system solutions has been pursued. One such solution is a silicon carrier-based System-on-Package (SOP) that enables high-density interconnection of heterogeneous die beyond current first level packaging densities. Silicon carrier packaging contains through silicon vias (TSV), fine pitch Cu wiring and high-density solder pads/joins, all of which are compatible with traditional semiconductor methods and tools. These same technology elements, especially the through silicon via process, also enable three dimensional stacking and integration. An approach to fabricating electrical through-vias in silicon is described, featuring annular-shaped vias instead of the more conventional cylindrical via. This difference enables large-area, un...

Three-dimensional silicon integration

IBM Journal of Research and Development, 2000

Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned silicon, and silicon-to-silicon fine-pitch interconnections offers many product benefits. Advantages of these emerging 3D silicon integration technologies can include the following: power efficiency, performance enhancements, significant product miniaturization, cost reduction, and modular design for improved time to market. IBM research activities are aimed at providing design rules, structures, and processes that make 3D technology manufacturable for chips used in actual products on the basis of data from test-vehicle (i.e., prototype) design, fabrication, and characterization demonstrations. Three-dimensional integration can be applied to a wide range of interconnection densities (,10/cm 2 to 10 8 /cm 2 ), requiring new architectures for product optimization and multiple options for fabrication. Demonstration test structures, which are designed, fabricated, and characterized, are used to generate experimental data, establish models and design guidelines, and help define processes for future product consideration. This paper 1) reviews technology integration from a historical perspective, 2) describes industry-wide progress in 3D technology with examples of TSV and silicon-silicon interconnection advancement over the last 10 years, 3) highlights 3D technology from IBM, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and 4) provides examples of 3D emerging industry product applications that could create marketable systems.

3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections

Ibm Journal of Research and Development, 2008

Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies. There are several approaches for 3D chip stacking including chip to chip, chip to wafer, and wafer to wafer. Chip-to-chip integration and chip-to-wafer integration offer the ability to stack known good dies, which can lead to higher yields without integrated redundancy. In the future, with structure and process optimization, wafer-to-wafer integration may provide an ultimate solution for the highest manufacturing throughput assuming a high yield and minimal loss of good dies and wafers. In the near term, chip-to-chip and chip-to-wafer integration may offer high yield, high flexibility, and high performance with added timeto-market advantages. In this work, results are reported for 3D integration after using a chip-to-wafer assembly process using 3D chip-stacking technology and fine-pitch interconnects with leadfree solder. Stacks of up to six dies were assembled and characterized using lead-free solder interconnections that were less than 6 lm in height. The average resistance of the TSV including the lead-free solder interconnect was as low as 21 mX.

3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias

IEEE Journal of Solid-state Circuits, 2006

System-on-Chip (SOC) and System-on-Package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS technology densities, a range of two-and three-dimensional silicon integration technologies are emerging which will likely support next-generation high-volume electronic applications and may serve high-performance computing applications. This paper will discuss a few emerging technologies which offer opportunities for enhanced circuit performance, or reduced power as one example.

Low-cost TSH (through-silicon hole) interposers for 3D IC integration

2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 2014

In this investigation, a SiP (system-in-package) which consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top- and bottom-side (a real 3D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top-chip, bottom-chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be preformed to demonstrate the integrity of the SiP structure.

Through-Silicon Via Technology for 3D Applications-an Invited Talk

The development, characterization, and implementation of electrodeposition processes for IMEC's 3D-WLP flow on 200 mm wafer level is reported. The flow comprises of polymer-isolated Through-Silicon Vias (TSVs), realized on thinned wafers bonded to temporary carriers. Defect-free filling of 25 × 50 µm TSVs with copper was achieved, using IMEC ViaFill chemistry. Copper deposition and a subsequent tin plating in the same process step enables one to create µ-bumps, which then allow for the formation of interconnects between stacked dies. A method is proposed for studying the filling quality by preparing slanted cross-sections by mechanical polishing, which are subsequently inspected using optical microscopy. With this method, one can reveal defects at different levels inside the via and it has the advantage that a large number of TSVs are analysed. In addition to sectioning, an electrical characterization was done on both stacked dies and daisy chains and via chain connectivity is demonstrated.

Through-Silicon Hole Interposers for 3-D IC Integration

IEEE Transactions on Components, Packaging and Manufacturing Technology, 2014

In this investigation, a system-in-package (SiP) that consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top and bottom sides (a real 3-D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top chip, bottom chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be performed to demonstrate the integrity of the SiP structure.

Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits

Microelectronics Journal, 2010

The integration of chips in the third dimension has been explored to address various physical and system level limitations currently undermining chip performance. In this paper, we present a comprehensive analysis of the electrical properties of through silicon vias and microconnects with an emphasis on single via characteristics as well as inter-TSV capacitive and inductive coupling in the presence of either a neighboring ground tap or a grounded substrate back plane. We also analyze the impact of technology scaling on TSV electrical parasitics, and investigate the power and delay trend in 3-D interstratum IO drivers with those of global wire in 2-D circuits over various technology nodes. We estimate the global wire length necessary to produce an equivalent 3-D IO delay, a metric useful in early stage design tools for 3D floorplanning that considers the electrical characteristics of 3D connections with TSVs and microconnects.