Performance Evaluation of Novel Strain-Engineered Ge-InGaAs Heterojunction Tunnel Field-Effect Transistors (original) (raw)
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IEEE Journal of the Electron Devices Society, 2015
The structural, morphological, and energy band alignment properties of biaxial tensile-strained germanium epilayers, grown in-situ on GaAs via a linearly graded In x Ga 1−x As buffer architecture and utilizing dual chamber molecular beam epitaxy, were investigated. Precise control over the growth conditions yielded a tunable in-plane biaxial tensile strain within the Ge thin films that was modulated by the underlying In x Ga 1−x As "virtual substrate" composition. In-plane tensile strains up to 1.94% were achieved without Ge relaxation for layer thicknesses of 15 to 30 nm. High-resolution x-ray diffraction supported the pseudomorphic nature of the Ge/In x Ga 1−x As interface, indicating a quasi-ideal stress transfer to the Ge lattice. High-resolution transmission electron microscopy revealed defect-free Ge epitaxy and a sharp, coherent interface at the Ge/In x Ga 1−x As heterojunction. Surface morphology characterization using atomic force microscopy exhibited symmetric, 2-D cross-hatch patterns with root mean square roughness less than 4.5 nm. X-ray photoelectron spectroscopic analysis revealed a positive, monotonic trend in band offsets for increasing tensile strain. The superior structural and band alignment properties of strain-engineered epitaxial Ge suggest that tensile-strained Ge/In x Ga 1−x As heterostructures show great potential for future high-performance tunnel field-effect transistor architectures requiring flexible device design criteria while maintaining low power, energy-efficient device operation.
Journal of Applied Physics, 2014
Group IV based tunnel field-effect transistors generally show lower on-current than III-V based devices because of the weaker phonon-assisted tunneling transitions in the group IV indirect bandgap materials. Direct tunneling in Ge, however, can be enhanced by strain engineering. In this work, we use a 30-band k Á p method to calculate the band structure of biaxial tensile strained Ge and then extract the bandgaps and effective masses at C and L symmetry points in k-space, from which the parameters for the direct and indirect band-to-band tunneling (BTBT) models are determined. While transitions from the heavy and light hole valence bands to the conduction band edge at the L point are always bridged by phonon scattering, we highlight a new finding that only the light-holelike valence band is strongly coupling to the conduction band at the C point even in the presence of strain based on the 30-band k Á p analysis. By utilizing a Technology Computer Aided Design simulator equipped with the calculated band-to-band tunneling BTBT models, the electrical characteristics of tensile strained Ge point and line tunneling devices are self-consistently computed considering multiple dynamic nonlocal tunnel paths. The influence of field-induced quantum confinement on the tunneling onset is included. Our simulation predicts that an on-current up to 160 (260) lA/lm can be achieved along with on/off ratio > 10 6 for V DD ¼ 0.5 V by the n-type (p-type) line tunneling device made of 2.5% biaxial tensile strained Ge. V
Applied Physics Letters, 2013
In this letter, we propose a heterostructure design for tunnel field effect transistors with two low direct bandgap group IV compounds, GeSn and highly tensely strained Ge in combination with ternary SiGeSn alloy. Electronic band calculations show that strained Ge, used as channel, grown on Ge1−xSnx (x > 9%) buffer, as source, becomes a direct bandgap which significantly increases the tunneling probability. The SiGeSn ternaries are well suitable as drain since they offer a large indirect bandgap. The growth of such heterostructures with the desired band alignment is presented. The crystalline quality of the (Si)Ge(Sn) layers is similar to state-of-the-art SiGe layers.
Tensile-Strained Nanoscale Ge/In0.16Ga0.84As Heterostructure for Tunnel Field-Effect Transistor
ACS Applied Materials & Interfaces, 2014
Tensile strained Ge/In 0.16 Ga 0.84 As heterostructure was grown in situ by molecular beam epitaxy using two separated growth chambers for Ge and III−V materials. Controlled growth conditions led to the presence of 0.75% in-plane tensile strain within Ge layer. High-resolution transmission electron microscopy confirmed pseudomorphic Ge with high crystalline quality and a sharp Ge/In 0.16 Ga 0.84 As heterointerface. Atomic force microscopy revealed a uniform two-dimensional cross-hatch surface morphology with a root-mean-square roughness of 1.26 nm. X-ray photoelectron spectroscopy demonstrated reduced tunnelingbarrier-height compared with Ge/GaAs heterostructure. The superior structural properties suggest tensile strained Ge/In 0.16 Ga 0.84 As heterostructure would be a promising candidate for high-performance and energy-efficient tunnel field-effect transistor applications.
Uniform strain in heterostructure tunnel field-effect transistors
IEEE Electron Device Letters, 2016
Strain can strongly impact the performance of III-V tunnel field-effect transistors (TFET). However, previous studies on homostructure TFETs have found an increase in on-current to be accompanied with a degradation of subthreshold swing. We perform 30-band quantum mechanical simulations of staggered heterostructure p-n-in tunnel field-effect transistors submitted to uniaxial and biaxial uniform stress and find the origin of the subthreshold degradation to be a reduction of the density of states in the strained case. We apply an alternative configuration including a lowly doped pocket in the source which allows to take full benefit of the strain-induced increase in on-current. Index Terms-TFET, strain, heterostructure B AND-TO-BAND tunneling (BTBT) allows the tunnel field-effect transistor (TFET) to obtain a sub-60 mV/dec subthreshold swing (SS) at room temperature [1]-[3]. This enables a reduction of supply voltage, making the TFET a promising alternative to the conventional metal-oxidesemiconductor field-effect transistor (MOSFET) for future low-power applications. The challenge consists, however, in sustaining the sub-60 mV/dec SS up to sufficiently high currents. Recent research has therefore proposed various improvements to the classic Si p-in TFET design in the form of dopant pockets [4], [5], alternative gate positioning and composition [6]-[8], a change in material to III-V compounds and the introduction of a heterostructure [9]-[14]. Strain engineering is another way to influence TFET performance through its effect on the band structure. In current MOSFET technology, the application of strain has become an invaluable asset to increase carrier mobilities [15]. For TFET, the effect of strain on the tunneling current has been simulated [16], [17] and measured [18]-[21] in group-IV configurations, with biaxial tensile strain turning out beneficial for the oncurrent (I ON) and SS. For III-V TFETs, strain research is more scarce. 8-band k•p simulation studies have predicted a beneficial effect on I ON for biaxial tensile strain, both in InAs homostructure [22] and broken-gap GaSb/InAs heterostructure TFETs [23]. However, in both cases the SS was found to deteriorate with increasing tensile strain.
Tensile-Strained Nanoscale Ge/In 0.16 Ga 0.84 As Heterostructure for Tunnel Field-Effect Transistor
ACS Applied Materials & Interfaces, 2014
Tensile strained Ge/In 0.16 Ga 0.84 As heterostructure was grown in situ by molecular beam epitaxy using two separated growth chambers for Ge and III−V materials. Controlled growth conditions led to the presence of 0.75% in-plane tensile strain within Ge layer. High-resolution transmission electron microscopy confirmed pseudomorphic Ge with high crystalline quality and a sharp Ge/In 0.16 Ga 0.84 As heterointerface. Atomic force microscopy revealed a uniform two-dimensional cross-hatch surface morphology with a root-mean-square roughness of 1.26 nm. X-ray photoelectron spectroscopy demonstrated reduced tunnelingbarrier-height compared with Ge/GaAs heterostructure. The superior structural properties suggest tensile strained Ge/In 0.16 Ga 0.84 As heterostructure would be a promising candidate for high-performance and energy-efficient tunnel field-effect transistor applications.
Sub10-nm Tunnel Field-Effect Transistor With Graded Si/Ge Heterojunction
IEEE Electron Device Letters, 2011
This study presents a new sub-10-nm tunnel field-effect transistor (TFET) with bandgap engineering using a graded Si/Ge heterojunction. Both the height and width of the tunneling barrier are highly controlled by applying gate voltages to ensure a near ideal sub-5-mV/dec switching of scaled sub-10-nm TFETs at 300 K. This study performed a 2-D simulation to elucidate p-body graded Si/Ge heterojunction TFET devices from 50 to 5 nm. The on-state tunneling barrier around the source was narrowed and lowered to demonstrate a high on-current; simultaneously, the off-state tunneling barrier was raised and extended into the drain to control the short-channel effect and ambipolar leakage current. The shorter the length is, the more abrupt is the switching. The breakthrough in subthreshold swing and short-channel effect make the graded Si/Ge TFET highly promising as an ideal green transistor into sub-10-nm regimes.
Design of Si 0.5 Ge 0.5 based tunnel field effect transistor and its performance evaluation
Band to band tunneling (BTBT) Tunnel field effect transistor (TFET) a b s t r a c t In this work, the performance comparison of two heterojunction PIN TFETs having Si channel and Si 0.5 Ge 0.5 source with high-k (SiGe DGTFET HK) and hetero-gate dielectric (SiGe DGTFET HG) respectively with those of two homojunction Si based PIN (DGTFET HK and DGTFET HG) TFETs is performed. Similarly, by employing the technique of pocketing at source junction in above four PIN TFETs, the performances of resultant four PNPN TFETs (SiGe PNPN DGTFET HK, SiGe PNPN DGTFET HG, PNPN DGTFET HK and PNPN DGTFET HG) are also compared with each other. Due to lower tunnel resistance of SiGe based hetero-junction PIN and PNPN TFETs, the DC parameters such as ON current, ON-OFF current ratio, average subthreshold slope are improved significantly as compared to Si based PIN and PNPN TFETs respectively. The output characteristics of HG architectures in Si based homojunction PIN and PNPN TFETs is observed to be identical to with respective Si based HK PIN and PNPN TFET architectures. However, the output characteristics of HG archi-tectures in SiGe based heterojunction PIN and PNPN TFETs degrade as compared to their respective SiGe based HK PIN and PNPN TFET architectures. In ON state, SiGe based HK and HG PIN and PNPN TFETs have lower gate capacitance (C gg) as compared to their respective Si based HK and HG PIN and PNPN TFETs. Moreover, HG architecture suppresses gate to drain capacitance (C gd) and ambipolar conduction. Transconductance (g m) and cut off frequency (f T) is also observed to be higher for SiGe based PIN and PNPN TFETs.
2011
Compressively strained Si 1-x Ge x band-to-band tunneling field effect transistors with planar structure and HfO 2 /TiN gate stack have been produced and analyzed, with different Germanium concentrations of x = 0.35, 0.50 and 0.65. Simulations using a nonlocal band-toband-tunneling model have been carried out to understand the switching behavior and its dependence on the material parameters. One would expect an increase of the tunneling currents for the increase of x. However, the Si 0.5 Ge 0.5 devices show the highest I on and smallest S, whereas Si 0.35 Ge 0.65 devices exhibit decreased currents due to partial strain relaxation.
IEEE Transactions on Electron Devices, 2006
Large band-to-band tunneling (BTBT) leakage currents can ultimately limit the scalability of high-mobility (smallbandgap) materials. This paper presents a novel heterostructure double-gate FET (DGFET) that can significantly reduce BTBT leakage currents while retaining its high mobility, making it suitable for scaling into the sub-20-nm regime. In particular, through one-dimensional Poisson-Schrodinger, full-band Monte Carlo, and detailed BTBT simulations, the tradeoffs between carrier transport, electrostatics, and BTBT leakage in high-mobility sub-20-nm Si-strained SiGe-Si (high germanium concentration) heterostructure PMOS DGFETs are thoroughly analyzed. The results show a dramatic (> 100×) reduction in BTBT and an excellent electrostatic control of the channel while maintaining very high drive currents and switching frequencies in these nanoscale transistors.