Optimal control of rapid thermal annealing in a semiconductor process (original) (raw)

Optimal iterative learning control of wafer temperature uniformity in rapid thermal processing

Proceedings of the 15th IFAC World Congress, 2002, 2002

An optimal iterative learning control (ILC) technique based on a quadratic optimal criterion has been implemented and evaluated in an experimental rapid thermal processing (RTP) system fabricating 8-inch silicon wafers. The control technique is based on a time-varying linear state space model which approximates a nonlinear system along a reference trajectory. This ILC control technique is capable of making improvements in the control performance from one run to next and eventually converges to a minimum achievable tracking error despite model error. Through a series of experiments with wafers on which thermocouples are glued, it was observed that the wafer temperatures are steered to the reference trajectory reducing the differences overcoming various disturbances.

Optimization of temperature-time profiles in rapid thermal annealing

1999

Rapid thermal annealing (RTA) is widely used in modern IC technology to reduce the amount of transient enhanced diffusion (TED) of dopants after ion implantation. The effect of diffusion reduction due to fast temperature ramping (50°C/s and above) and short annealing times (less than 10 seconds at 1000°C) is well known. However, a systematic investigation of TED over a broad range of temperature-time conditions can, to the authors' best knowledge, not be found in the literature yet. In this simulation study we investigate phosphorus TED between 600°C and 1100°C for annealing times from a few seconds to several hours

Heat Transfer Process Control in Integrated Circuits at Nano Meter Sizes

Procedia Materials Science, 2015

The advent of new nanometer process technologies has made it possible to integrate billions of transistors on a single chip. The increase in functionality coupled with decrease in size has resulted in more power consumption and this increases the need for a better and efficient power dissipation. This is resulting in significant amount of leakage currents flowing into the substrate made up of Silicon. This is resulting in increase in substrate heating and the thermal noise thus generated is coupling with the other signals. In this paper optimization of the Sherwood parameter has been carried and its effect on controlling the substrate heating is studied.

Ultra-shallow junction by laser annealing: Integration issues and modelling

Nuclear Instruments and …, 2006

A revolutionary approach to the technology design is required for the integration of the laser annealing process in nano-electronic device fabrication. The list of the integration issues includes: the patterning effect, the extreme non-equilibrium kinetics of dopant and defects, the material modification due to the melting-regrowth phenomena (in the melting regime) and the residual damage problem. The intense research effort required surely benefits from an adequate development of dedicated technology computer aided design tools. We present the computational apparatus needed for the simulation of the laser annealing process in Si-based devices. The tools aim at the simulation at a different resolution (from the atomic to the continuum level) of the phenomena occurring inside the specimen during the irradiation. The usage impact of such simulation tools on the process integration is conclusively crucial for a reliable device design and the final optimisation of fabricated MOS transistors.

ADVANCED ANNEALING FOR SUB130nm JUNCTION FORMATION

This paper will discuss a new lamp annealing technique called Flash-assist RTP (fRTP™) that operates in the large gap in process time between laser thermal processing and conventional RTP. It has shown promising results with both Pand N-type junctions easily meeting the 60 nm technology node requirements as defined by ITRS2000. fRTP overcomes one of the fundamental limitations of lamp-heated Rapid Thermal Processing: it is very difficult to heat, and especially, cool the bulk of a wafer. In fRTP, the bulk of the wafer is heated to an intermediate temperature using fairly conventional RTP, but then the device side of the wafer is exposed to a short (order of 1 -10 ms) pulse or flash of intense light. The flash raises a thin layer of the wafer to a higher temperature. Since the flash duration is short compared to the thermal time constant of the wafer, the bulk of the wafer is not significantly heated. Once the flash energy is removed, the bulk of the wafer acts as a heat sink to very quickly cool the heated layer. If the intermediate temperature and temperature "jump" of the front side are chosen correctly, very high electrical activation occurs with very little dopant diffusion or change in junction depth from the as implanted position. The independent control of the flash conditions and intermediate temperature gives flexibility in junction engineering.

Corrective feed-back control of the annealing process with utilization of the indirect measurement

Proceedings of the 2011 12th International Carpathian Control Conference, ICCC'2011, 2011

In this contribution is described corrective feedback control of the steel roll's annealing process based on behavior of inner temperature in the roll with utilization of indirect measurement system of the inner steel roll temperatures. Indirect measurement system of the inner temperatures indirect measures temperature inside the roll that is not measurable without destruction of the roll, from direct measured temperature of the atmosphere. Indirect measured temperature inside the roll in chosen place (coolest place in the roll) is as input to the algorithm of the corrective feedback control. This control adjusts atmosphere temperature for next control step, based on error calculation between required inner temperature and indirect measured inner temperature.

Dependence of junction depth and sheet resistance on the thermal budget in the low temperature pre-stabilization regime

SCS 2003 International Symposium on Signals Circuits and Systems Proceedings (Cat No 03EX720) IIT-02, 2002

Roadmap for Semiconductors (ITRS) one of the key challenges for source/drain extension technology at the 100 nm technology node and beyond is to produce a junction in the range of a few tens of nanometers with low sheet resistance values. To achieve the requirements of the ITRS, a deep understanding of the diffusion, activation and the dopant-defect interaction is necessary. In this paper the temperature-time profile of spike anneals is varied. The temperature of the pre-stabilization step was set between 600°C and 800°C for 10 s. The pre-stabilization step was followed by a constant spike-annealing condition to achieve high electrical activation, and for reference each prestabilization condition was also used to process wafers without additional spike-annealing. The effects of these variations in the thermal budget in the low temperature regime were evaluated for the implant species 11 B + and 49 BF 2 + and for diverse implant energies and doses. All the data are analyzed and discussed with respect to the junction depth versus sheet resistance figure. With the pre-stabilization at 650°C for 10 s followed by the spike anneal the best results with respect to junction depth and sheet resistance are achieved.

Flash Annealing Technology for USJ: Modeling and Metrology

2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2006

Millisecond annealing either by flash lamp or laser appears to be the leading approach to meet the needs of ultra-shallow junction annealing and polysilicon activation for advanced technology nodes. There are many advantages to this technology including high electrical activation, excellent lateral abruptness, controlled and limited dopant diffusion and the ability to engineer the extended defects remaining from the ion implantation. There are also many challenges such as potential pattern effects, local and global wafer stress and difficulty in process integration. Additional challenges include the need to extend the capabilities of process TCAD to allow accurate simulation and prediction of the ms processes. Modeling of diffusion, activation and defect evolution for a variety of technologically interesting doping conditions must be dependable to allow the device designer and process engineer to predict the device behavior after ms annealing. Existing models fall short or still need to be validated. Metrology for ultra-shallow junctions is also a challenge. The ability to accurately and repeatably measure sheet resistance and junction leakage on junctions of the order of 10nm deep is very difficult. This paper will provide an overview of flash lamp annealing and deal with some promising extensions of process simulation to enable the predictive modeling of junction behavior under flash lamp annealing conditions. We will also examine some of the new metrology techniques for characterization of these very shallow junctions and look at some of the trends exhibited for different junction formation details.

Performance evaluation of run-to-run control methods in semiconductor processes

2003

Run-to-Run (RtR) control plays an important role in semiconductor manufacturing processes. In this paper, RtR control methods are classified and evaluated. The set-valued RtR controllers sith ellipsoid approximation are compared with two typical RtR controllers: the Exponentially Weighted Moving Average (EWMA) controller and the Optimizing Adaptive Quality Controller (OAQC) by simulations according to the following criteria: A good RtR controller should be able to compensate for various disturbances, such as small drifts, step disturbances and model errors; moreover, it should he able to deal with hounds, cost requirement and multiple targets that are often encountered in semiconductor processes. Based on our simulation results, suggestions on selection of a proper RtR controller for a semiconductor process are given as conclusions.