Preliminaries on a Hardware-Based Approach to Support Mixed-Critical Workload Execution in Multicore Processors (original) (raw)
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20th IEEE Latin American Test Symposium - LATS 2019, 2019
The use of multicore processors in generalpurpose real-time embedded systems has experienced a huge increase in recent years. Unfortunately, critical applications are not benefiting from this type of processors as one could expect. The major obstacle is that we may not predict and provide any guarantee on real-time properties of software running on such platforms. The shared memory bus is among the most critical resources, which severely degrades the timing predictability of multicore software due to the bus access contention between cores. To counteract this problem, we present in this paper a new approach that supports mixed-criticality workload execution in a multicore processor-based embedded system. It allows any number of cores to run less-critical tasks concurrently with the critical core, which is running the critical task. The approach is based on the use of an infrastructure intellectual property (I-IP) core named Deadline Enforcement Checker (DEC) implemented in hardware, which allows the execution of any number of cores (running less-critical workloads) concurrently with the critical core (executing the critical workload). This approach allows the exploitation of the maximum performance offered by a multiprocessing system while guaranteeing critical task schedulability, i.e., that the critical task execution will not violate timing deadline. A case-study based on a dual-core version of the LEON3 softcore processor was implemented in VHDL language. Practical experiments demonstrate the proposed technique is very effective on combining system high performance with critical task schedulability within timing deadline.
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Modern safety-critical systems, such as avionics, tend to be mixed-critical, because integration of different tasks with different assurance requirements can effectively reduce their costs in terms of hardware, at the risk, however to increase the costs for certification, in particular in the context of proving their schedulability. To simplify the certification costs such systems use Time Triggered (TT) scheduling paradigm, and a generalization of the Time Triggered (TT) scheduling paradigm Single Time Mode (STTM). We present a state-of-the art STTM algorithm which works optimally on single core and shows good experimental results for multi-cores. In addition, because the algorithm can be applied on top of any memoryless scheduling policy, we show that applying it to list scheduling leads to support of task graph (precedence) dependencies and/or non-preemptive scheduling, for which our algorithm also shows good experimental results.
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To manage the complexity of concurrent-system design, the applications running in the nodes of distributed systems have to be designed in an appropriate high-level model of computation (MoC). In addition, for systems that are timing-critical and compute-intensive, it may be required to introduce so-called mixed-critical resource managers (dynamic scheduling policies) that adapt system resource usage to critical run-time situations (eg overheating, overload, hardware errors) by giving the highly critical subset of system functions priority over low-critical ones in emergency situations. However, especially for modern platforms-multi-and many-cores-it is highly non-trivial to manage resources not only because of their inherent parallelism but also because of ``parasitic'' interference between the cores due to shared hardware resources (buses, FPU's, DMA's, etc). To close the semantical gap between MoCs on one side and resource managers on the other, we compile the MoCs into expressive automata-based language, used to validate and implement a given MoC/resource manager combination. In this context, we present our current work-in-progress on scheduling tools for handling the multi-core interference in mixed-critical applications.
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Real-time systems are increasingly running a mix of tasks with different criticality levels: for instance, unmanned aerial vehicle has multiple software functions with different safety criticality levels, but runs them on a single, shared computational platform. In addition, these systems are increasingly deployed on multiprocessor platforms because this can help to reduce their cost, space, weight, and power consumption. To assure the safety of such systems, several mixed-criticality scheduling algorithms have been developed that can provide mixed-criticality timing guarantees. However, most existing algorithms have two important limitations: they do not guarantee strong isolation among the high-criticality tasks, and they offer poor real-time performance for the low-criticality tasks.
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This paper investigates real-time scheduling algorithms on upcoming multithreaded processors. As evaluation testbed we introduce a multithreaded processor kernel which is specifically designed as core processor of a microcontroller or system-on-a-chip. Handling of external realtime events is performed through multithreading. Real-time threads are used as interrupt service threads (ISTs) instead of interrupt service routines (ISRs). Our proposed microcontroller supports multiple ISTs with zero-cycle context switching overhead. We investigate the behavior of fixed priority preemptive, earliest deadline first, least laxity first and guaranteed percentage scheduling with respect to multithreaded processors. Our finding is that the strategies GP and LLF result in a good blending of instructions of different threads thus enabling a multithreaded processor to utilize latencies best. Assuming a zero-cycle context switch LLF performs best, however implementation cost are prohibitive.
An architecture for the simultaneous execution of hard real-time threads
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Simultaneous multithreading (SMT) processors might be good candidates to fulfill the ever increasing performance needs of embedded applications. However, off-theshelves SMT architectures do not fit the timing predictability requirements of hard real-time systems: to schedule critical threads so that they are guaranteed to meet their deadlines, it is necessary to estimate their Worst-Case Execution Times which is not possible when simultaneous threads might interfere. In this paper, we propose an SMT architecture designed to enforce isolation between hard real-time threads so that their worst-case execution time can be safely estimated. We report experimental results that show that this architecture still provides a high level of performance and we give an insight into how the thread isolation feature could be controlled by a real-time task scheduler. I.
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Real-time embedded systems that combine processes of various criticalities (i.e. mixed-criticality real-time systems) represent an emerging research that faces many issues. This paper describes a new ASIC design of a coprocessor that realizes process scheduling for mixed-criticality real-time systems. The solution proposed in this paper uses Robust Earliest Deadline (RED) algorithm. Due to the on-chip implementation of the scheduler, all scheduler operations always take two clock cycles to execute. The proposed solution was verified by simulations that applied millions of random inputs. Chip area costs are evaluated by synthesis into ASIC using 28 nm TSMC technology. The proposed RED-based scheduler is compared with an existing EDF-based scheduler that supports hard realtime processes only. Even though the RED-based scheduler costs more chip area, it can handle any combinations of process criticalities, variations of process execution times and deadlines, achieves higher CPU utilization and can be used for scheduling of non-real-time, soft real-time and hard real-time processes combined within one system.
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In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architectures suitable for use in embedded systems. However, since threads share many resources, they also interfere with each other. As a result, execution times of applications become highly unpredictable and dependent on the context in which an application is executed. Obviously, this poses problems if an SMT is to be used in a real-time system.
New Insights Into the Real-Time Performance of a Multicore Processor
IEEE Access, 2020
Multicore processors are gaining popularity in various domains because of their potential for maximizing system throughput of average-case tasks. In real-time systems, where processes and tasks are governed by stringent temporal constraints, the worst-case timings should be considered, and migration to multicore processors leads to additional difficulties. Resource sharing between the cores introduces timing overheads, which affect the worst-case timings and schedulability of the entire system. In this article, we provide new insights into the performance of the real-time extensions of Linux, namely, Xenomai and RT-Preempt, for a homogeneous multicore processor. First, complete details on leveraging both real-time extensions are presented. We identify various multicore deployments and discuss their trade-offs, as established through the experimental evaluation of the scheduling latency. Then, we propose a statistical method based on a variation of chi-square test to determine the best multicore deployment. The unexpected effects of interfering loads, such as CPU, memory, and network operations, on the real-time performance, are considered. Feasibility of the best multicore deployment is verified through the analysis of its periodicity and deterministic response times in a pre-emptive multitasking environment. This research is the first of its kind and will serve as a useful guideline for developing real-time applications on multicore processors.
Reserving Processors by Precise Scheduling of Mixed-Criticality Tasks
2021 IEEE 27th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), 2021
Mixed-criticality (MC) scheduling has been proposed to mitigate the pessimism in real-time schedulability analysis that must provide guarantees for the worst case. In most existing work on MC scheduling, low-critical tasks are either dropped or degraded at the criticality mode switch in order to preserve the temporal guarantees for high-critical tasks. Recently, a different direction, called precise MC scheduling, has been investigated. In precise MC scheduling, no low-critical task should be dropped or degraded; instead, the platform processing capacity is augmented at mode switch to accommodate the additional workload by high-critical tasks. In contrast to prior work on this topic with respect to varying processor speed, this work investigates the precise scheduling problem of MC tasks when the number of available processors may vary at the mode switch. To address this new problem, we propose two alternative algorithms by adapting virtual-deadline-based EDF and by fluid scheduling, respectively, and provide a sufficient schedulability test for each. We also conduct schedulability experiments with randomly generated task sets to demonstrate the effectiveness of the proposed algorithms and the benefits of the new scheduling model. Index Terms-mixed-criticality tasks, precise scheduling, reserving processors, virtual deadlines, fluid scheduling.