Inverted Gate Vedic Multiplier in 90nm CMOS Technology (original) (raw)
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Design of Low Power Vedic Multiplier Based on Reversible Logic
Reversible logic is a new technique to reduce the power dissipation. There is no loss of information in reversible logic and produces unique output for specified inputs and vice-versa. There is no loss of bits so the power dissipation is reduced. In this paper new design for high speed, low power and area efficient 8-bit Vedic multiplier using Urdhva Tiryakbhyam Sutra (ancient methodology of Indian mathematics) is introduced and implemented using Reversible logic to generate products with low power dissipation. UT Sutra generates partial product and sum in single step with less number of adders unit when compare to conventional booth and array multipliers which will reduce the delay and area utilized, Reversible logic will reduce the power dissipation. An 8-bit Vedic multiplier is realized using a 4-bit Vedic multiplier and modified ripple carry adders. The proposed logic blocks are implemented using Verilog HDL programming language, simulation using Xilinx ISE software.
Implementation of Low Power and Area Efficient Vedic Multiplier
International Journal of Innovative Technology and Exploring Engineering, 2019
Designing a low power consuming and area efficient Vedic Multiplier using Hybrid Full Adder. In this paper, Conventional CMOS (CCMOS) Full Adders involved in a conventional Vedic multiplier is replaced with Hybrid Full adders to achieve reduction in power consumption and area. In the proposed system ripple carry adders involved in Vedic multiplier are designed using Hybrid Full Adder. The design is done for 2-bit and it is extrapolated to 16-bit. Performance parameters such as power consumed and area between Vedic multiplier involving CCMOS and Hybrid Full Adder is done and a comparative study over them is made. Significant improvement is achieved in this implementation and the layout design is also implemented for the 2-bit, 4-bit, 8-bit and 16-bit Vedic multiplier for both Conventional CMOS and Hybrid Full-Adder logic styles. The implementation is carried out using Tanner EDA tool under 250-nm technology.
VLSI ARCHITECTURE OF AN 8-BIT MULTIPLIER USING VEDIC MATHEMATICS IN 180NM TECHNOLOGY
A Multiplier is one of the key hardware blocks in most fast processing system which requires less power dissipation. A conventional multiplier consumes more power. This paper presents a low power 8 bit Vedic Multiplier (VM) based on Vertically & Crosswise method of Vedic mathematics, a general multiplication formulae equally applicable to all cases of multiplication. It is based on generating all partial products and their sum in one step. The implementation is done using cadence Virtuoso tool. The power dissipation of 8x8 bit Vedic multiplier obtained after synthesis is compared with conventional multipliers such as Wallace tree and array multipliers and found that the proposed Vedic multiplier circuit seems to have better performance in terms of power dissipation.
A Transistor Level Analysis for a 8-BIT Vedic Multiplier
International Journal of Electronics Signals and Systems, 2012
Power and area efficient multiplier using CMOS logic circuits for applications in various digital signal processors is designed. This multiplier is implemented using Vedic multiplication algorithms mainly the "Urdhvatiryakbhyam sutra" , which is the most generalized one Vedic multiplication algorithm [1] . A multiplier is a very important element in almost all the processors and contributes substantially to the total power consumption of the system. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably compared with any conventional method . The schematic for this multiplier is designed using TANNER TOOL. The design is then verified in T-SPICE using 0.18 um CMOS technology library file. The analysis is made for various voltages across a range of 2.5V to 5V, to validate the design. A CMOS digital multiplier, with low power consumption and high linearity is proposed. The results prove that the proposed mu...
Design and Analysis of 8-bit Vedic Multiplier in 90nm Technology using GDI Technique
International Journal of Engineering & Technology, 2018
Vedic mathematics is an old mathematics which is more effective than other mathematic procedures. Vedic maths is utilized as a part of numerous applications, for example, hypothesis of numbers, compound duplications, squaring, cubing, square root and solid shape root and so on. Absolutely there are 16 sutras and 14 sub-sutras in Vedic maths. Among those sutras, just 3 sutras and 2 sub-sutras are utilized for augmentation. Multiplier is a very important part of a microprocessor as multiplication is performed continuously in all calculative procedures. This paper is in importance of a 8-bit multiplier designed in 90 nm technology. Urdhva-Tiryakbyham is the sutra that is used for multiplication in Vedic mathematics. Actualizing the different scientific operations utilizing Vedic Mathematics causes us accomplish better speed, bring down unpredictability and higher execution.[2] The technique used is Gate Diffusion Input (GDI) which is a more refined way to design a circuit which less c...
IMPLEMENTATION OF HIGH SPEED LOW POWER VEDIC MULTIPLIER USING REVERSIBLE LOGIC
Multiplication is an operation much needed in Digital Signal processing for various applications. Here we present a high speed Vedic Multiplier which is efficient in terms of speed, making use of Urdhva Tiryagbhyam, a sutra for multiplication from vedic math’s. It is a simple architecture coupled with increased speed forms an unparalleled combination for serving any complex multiplication computation. Tagged with these highlights, power dissipation can be reduced by implementing this with reversible logic. Power dissipation is another important constraint in an embedded system which cannot be neglected. The Reversible Logic has received great attention in the past recent years due to its ability in reducing the power dissipation, which is the major concern in Digital Designing.
DESIGN OF LOW POWER AND HIGH SPEED GDI BASED 8-BIT VEDIC MULTIPLIER
ANVESAK, 2023
Multiplier is the common hardware block present in any processor. Speed and power consumption become very vital in multiplier design consideration to conserve energy. An 8 bit Vedic multiplier using GDI technique is designed in this paper. Multiplication of two numbers will take more time and many steps. To design the proposed multiplier the Vedic mathematics sutra called UT is used. Any logic circuit can be designed by using CMOS logic. The CMOS logic will consumes more area. The numbers of transistors in the circuit are reduced by using GDI logic. Thus the Vedic mathematics will reduce the delay and the GDI logic will reduce the transistors count in a circuit which in turn reduces the power.
Design of low power delay efficient Vedic multiplier using reversible gates
In early days of computers, multiplication was implemented generally with a sequence of addition, subtraction and shift operations. There exist many algorithms proposed in the literature to perform multiplication, each offering different advantages and having trade-off in terms of delay, circuit complexity, area occupied on-chip and power consumption. Latency is the major issue of computing a function. Simply it's a measure of how long the inputs to a device are stable is the final result available on outputs. Throughput is the measure of how many multiplications can be performed in a given period of time. The multiplier is not only a high delay block but also a major source of power dissipation. Normal multiplication process involves generation of partial products, the addition of partial products and finally, total product is obtained. So the performance of the multiplier depends on the number of partial products and the speed of the adder. The reversible computation is one field which assures zero power dissipation. Thus during the design of any reversible circuit, the delay is the only parameter that has to be taken care of. Hence reversible Urdhva Tiryakbhayam [UT] Multiplier had been proposed for reversible calculations. Vedic multiplier based on the Urdhva Tiryakbhayam algorithms provide the best results in terms of delay, area, and power.
International Journal of Computer Applications, 2017
Devices optimization for power and speed is a major issue in ultra low power applications. The evolution of the MOSFET has proven to be the best choice for next generation processes. Portable device should have good battery life.Processor speed depends mainly on the multiplier. Paper present the analysis of 4-bit multiplier using a Vedic Mathematics (Urdhva Tiryagbhyam sutra) and conventional multiplier with two different adders has been realized using carry look ahead adder and ripple carry adder. Comparative study of multipliers is done for low power requirement and high speed. The main purpose of the paper is to investigate the better adder and multiplication technique. It is observed that the conventional multiplier with Carry look ahead adder is stable and power efficient. Finfet based conventional multiplier with CLA adder is having 10 % less energy delay product than Finfet based VEDIC multiplier with CLA adder and 21.9 % less than FDSOI based conventional multiplier with CLA adder at supply voltage 0.9 V. The variation shows that Finfet based vedic multiplier with CLA adder is having less process variation than fdsoi based conventional multiplier with CLA adder
2013
Binary multiplier is one of the most time and power consuming architectures in an ALU. The performance efficiency of complex computations is determined by the multiplier algorithm used. Design of an efficient multiplier thus becomes important. An attempt has been made to implement an efficient multiplier using ancient computational techniques using charge recovery logic. This circuit is compared against the existing vedic multiplier circuits designed using conventional CMOS logic, to validate our claim. A 4 9 4 vedic multiplier using 2 N-2P type of charge recovery logic structure is implemented. The design and verification have been done using industry standard SPICE tools. The simulation results depict reduction in the average power consumption by 77.66 %.