A Low Power, 8-Bit, 5MS/s Digital to Analog Converter for Successive Approximation ADC (original) (raw)
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A 1.8‐V 8‐bit 20MS/s successive approximation register (SAR) analog‐to‐digital converter (ADC) implemented in TSMC 0.18‐um CMOS process is presented. By applying low input capacitance that reduces driving difficulty of the ADC, the proposed SAR ADC achieves less sampling time. Also, asynchronous control logic is used which doesn't require an external high frequency clock to drive ADC. Measured results show that at the supply voltage of 1.8 V and sampling rate of 20 MS/s, the proposed SAR ADC achieves a spurious‐free dynamic range (SFDR) of 55.1 dB, a signal‐to‐ noise and distortion ratio (SNDR) of 44.5 dB, an effective number of bits (ENOB) of 7.1 bits, a differential nonlinearity (DNL) of 0.81 LSB, an integral nonlinearity (INL) of 1.24 LSB and a power consumption of 588 μW. Including pads, the chip area is only 0.74 (0.86 x 0.86) mm 2 with a small ADC core area of 0.176 mm 2 .
REVIEW OF CAPACITIVE DAC BASED SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER
Analog to Digital converters are essential between analog and digital circuits. It is one of the most important building blocks in sensor node which digitize the analog environmental information we live in. Many different kinds of analog to digital converter architectures are available such as Flash Type, Integrating type, Pipelined, Time Interleaved and Successive Approximation type. Successive Approximation Register ADC has always been considered for optimizing its Parameters like Speed, Static and Dynamic Error, Power Consumption by a designing a new switching method of the capacitive structure of Digital Analog
Limitations of Switched-Capacitor Analog/Digital Converters with Reference Processing Units
Frequenz, 1993
This paper discusses the major limitations of an emerging new class of A/D converters (ADC's), namely those employing a separate reference processing unit (RPU) which is linked to a signal processing unit (SPU). Three circuits are basically investigated; the first is by Chen and Svensson [1], the second is by Yung and Chao [2], and the third is a modified version of the first with a novel RPU. The effects of the following parameters are investigated: op-amp dc gain, capacitor ratio-mismatch error, and charge injection of switches. These effects are assessed in terms of their corresponding absolute integral nonlinearity (INL). Pertinent formulae are derived, and the results of computer simulations are presented. Whenever possible, comparison is held among the circuits presented. Übersicht: Dieser Beitrag beschreibt die Grenzen eines neuen Typs von A/D-Umsetzern mit einem getrennten Referenzspannungsprozessor (RPU), der mit einer Signalprozessoreinheit (SPU) verbunden ist. Drei Schaltungen werden grundsätzlich untersucht. Die erste stammt von Chen und Svensson [1], die zweite von Yung und Chap [2], die dritte ist eine modifizierte Version der ersten mit einer neuartigen RPU. Die Auswirkungen folgender Parameter werden untersucht: Gleichspannungsverstärkung des Operationsverstärkers, Abweichungen im Kapazitätsverhältnis und von Schaltern verursachte Ladungsänderungen. Der Einfluß dieser Effekte auf die entsprechende Integrale Nichtlinearität (INL) wird dargestellt. Soweit möglich werden die Schaltungen miteinander verglichen.
A Low-Power, Small-Size 10-Bit Successive-Approximation ADC
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2005
A new Successive-Approximation ADC (Analog-to-Digital Converter) was designed which not only consumes little power, but also requires a small chip area. To achieve those goals, both comparator and internal DAC (Digital-to-Analog Converter) have been improved. The ADC was designed in a 1.2 µm CMOS double-poly double-metal n-well process. It performs 10-bit conversion with 67 dB SFDR. Power consumption and die area are 0.6 mW and 0.95 mm 2 , respectively. ADC was extensively simulated using Hspice to verify the desired performance.
Design of High Performance Successive Approximation Register Analog to Digital Converter
This thesis presents a 1.2 V 9-bit Successive approximation register (SAR) analog to digital converter (ADC) design dedicated to the low power applications. It uses a switchback switching scheme in the digital to analog converter (DAC) to reduce power consumption. This thesis work also includes a general discussion about ADCs followed by a brief one about SAR ADCs. This bachelor project report covers the implementation of the SAR ADC as well as background information and design of the control logic, comparator, capacitive array, and switches that meet our specifications.
An ultra low-power DAC with fixed output common mode voltage
AEU - International Journal of Electronics and Communications, 2018
A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (V cm) of the DAC remains fixed for all the digital codes. This feature helps a lot to improve the linearity of a typical SAR ADC and reduce the power consumption of comparator. The layout of the proposed DAC is very simple and easy to extend in contrast to the binary weighted CDACs where the layout needs lots of care and time. Several Monte-Carlo and Post-Layout simulations using CMOS 0.18 technology prove the benefits of the proposed CDAC. The proposed CDAC reduces the power consumption by 99.8% while enhances the speed and linearity of the comparator in a SAR ADC.
A 0.5-v 1--μW successive approximation adc
IEEE Journal of Solid-State Circuits, 2003
A successive approximation analog-to-digital converter (ADC) is presented operating at ultralow supply voltages. The circuit is realized in a 0.18m standard CMOS technology. Neither low-devices nor voltage boosting techniques are used. All voltage levels are between supply voltage and ground . A passive sample-and-hold stage and a capacitor-based digital-to-analog converter are used to avoid application of operational amplifiers, since opamp operation requires higher values for the lowest possible supply voltage. The ADC has signal-to-noise-and-distortion ratios of 51.2 and 43.3 dB for supply voltages of 1 and 0.5 V, at sampling rates of 150 and 4.1 kS/s and power consumptions of 30 and 0.85 W, respectively. Proper operation is achieved down to a supply voltage of 0.4 V.
IJERT-Design of Successive Approximation Analog to Digital Converter with Modified DAC
International Journal of Engineering Research and Technology (IJERT), 2014
https://www.ijert.org/design-of-successive-approximation-analog-to-digital-converter-with-modified-dac https://www.ijert.org/research/design-of-successive-approximation-analog-to-digital-converter-with-modified-dac-IJERTV3IS070861.pdf This paper presents successive approximation analog to digital converter with modification in DAC module, hence it is important to select right architecture. Successive approximation Analog to Digital Converter has been preferred in most of the application because of their compact circuitry as compared with other ADC which makes this SAR ADC inexpensive. It has been observed that power dissipation is high in digital to analog module. Hence modification is proposed in digital to analog (DAC) architecture to achieve excellent power efficiency for a relatively moderate resolution. This SAR ADC is designed in 0.18µm CMOS technology achieves 500 KS/s will be useful for high speed with medium resolution and low power consumption application.
Analog to Digital Converters (ADC): A Literature Review
E3S Web of Conferences
The signal processing is advancing day by day as its needs and in wireline/wireless communication technology from 2G to 4G cellular communication technology with CMOS scaling process. In this context the high-performance ADCs, analog to digital converters have snatched the attention in the field of digital signal processing. The primary emphasis is on low power approaches to circuits, algorithms and architectures that apply to wireless systems. Different techniques are used for reducing power consumption by using low power supply, reduced threshold voltage, scaling of transistors, etc. In this paper, we have discussed the different types and different techniques used for analog to digital conversion of signals considering several parameters.