Experimental investigation on efficiency and linearity of microwave Doherty amplifier (original) (raw)
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Microwave Doherty Power Amplifier for High Efficiency and Linearity
2006 International Workshop on Integrated Nonlinear Microwave and Millimeter-Wave Circuits, 2006
This paper explains the basic circuit configuration of microwave Doherty amplifier and additional design methods for wide bandwidth and high power applications. This paper also presents the recent experimental results of our group using the uneven power drive. Most of the previous works about microwave Doherty amplifier have employed identical input drives. In this works, two 1:1(2-way) and a 1:2(3-way) Doherty amplifiers are implemented at 2.14GHz center frequency using LDMOS with a peak envelope power of 180 watt and 285 watt, respectively. The 2-way Doherty amplifiers are optimized at 25 watt average output power for high efficiency and linearity and the 3-way Doherty amplifier at 16 watt average output power for high linearity. The amplifiers are tested using WCDMA 4FA signal. The performances of the 2-way Doherty amplifier are compared with that of the comparable class AB amplifier and the Doherty amplifier with even power drive. The performances of the 3-way Doherty amplifier are compared with that of the comparable class AB amplifier. The experimental results show the superior performances of our Doherty amplifiers.
A high efficiency Si LDMOS Doherty power amplifier with optimized linearity
2009 SBMO/IEEE MTT-S International Microwave and Optoelectronics Conference (IMOC), 2009
This paper presents a high efficiency uneven UMTS Doherty power amplifier (DPA) based on Si LDMOS technology. An optimum output combining network was designed to enhance the efficiency at backoff power. High efficiency Si LDMOS transistors were used for the DPA design. The designed DPA has a maximum output power of P sat =39.7 dBm (9.4 W). A maximum drain efficiency of η max =54 % (PAE max =40 %) was measured. The efficiency was maintained above η=40 % (PAE =36 %), over 6 dB backoff, and above η=32 % (PAE=30 %), over 9 dB backoff, relative to the maximum (saturated) output power. The designed PA was experimentally optimized to enhance its linearity. For a 1-carrier W-CDMA test signal, an ACPR of -44 dBc was measured at an average output power of P out =30.7 dBm.
2005 European Microwave Conference, 2005
We have proposed advanced design methods of Doherty amplifier for high efficiency base station power amplifiers with wide bandwidth. First, we develop Doherty amplifier with uneven power drive which is provided more input power to the peaking cell than the carrier cell for full power operation and appropriate load modulation. Second, we optimize the matching circuits of the carrier and peaking cells individually to enhance the linearity and efficiency. Third, we optimize the bias circuit to solve an asymmetric ACLR(Adjacent Channel Leakage Ratio) characteristics for wideband signals such as WCDMA 4FA. The proposed design methods are applied to implement Doherty amplifier using a MRF5P21180. For a 2.14 GHz WCDMA 4FA signal, the amplifier is optimized at 25 W average output power. The drain efficiency and ACLR measured at the power are 33 % and -41 dBc, which represent about 1.3 % and 3 dB improvements, respectively, compared to the Doherty amplifier with even power drive. Additionally, the PEP of the amplifier is about 180 W, while that of the comparable Doherty amplifier is about 165 W. The difference of ACLR with the bias circuit optimization between lower and upper ACLR is reduced below 2 dB at whole average output power range.
A Survey on RF and Microwave Doherty Power Amplifier for Mobile Handset Applications
Electronics
This survey addresses the cutting-edge load modulation microwave and radio frequency power amplifiers for next-generation wireless communication standards. The basic operational principle of the Doherty amplifier and its defective behavior that has been originated by transistor characteristics will be presented. Moreover, advance design architectures for enhancing the Doherty power amplifier’s performance in terms of higher efficiency and wider bandwidth characteristics, as well as the compact design techniques of Doherty amplifier that meets the requirements of legacy 5G handset applications, will be discussed.
IEEE Microwave and Wireless Components Letters, 2003
In this letter, we have demonstrated a microwave Doherty amplifier employing input signal envelope tracking technique. In the amplifier, gate bias of peaking amplifier is controlled according to the magnitude of the envelope. A 2.14-GHz Doherty amplifier has been implemented using 4-W PEP LDMOSFETs and an adaptive controlled gate bias circuit has been constructed and the control shape is optimized experimentally. The performance of the microwave Doherty amplifier has been compared with those of class AB amplifier using one-tone, two-tone, and forward-link wideband code-division multiple access (WCDMA) signals. For a forward-link WCDMA signal, the measured power added efficiency (PAE) of the microwave Doherty amplifier is 39.4% at 30 dBc adjacent channel leakage ratio (ACLR), while that of the comparable class AB amplifier is 24.2% at the same ACLR level. Index Terms-Adjacent channel leakage ratio (ACLR), envelope tracking, microwave Doherty amplifier, power added efficiency (PAE), wideband code-division multiple access (WCDMA).
High Efficiency Doherty Power Amplifier Historical Aspect and Modern Trends
This overview of the Doherty amplifier covers broadband capabilities of a two-stage amplifier, conventional Doherty architectures, a digitally driven Doherty technique, and the amplifier applied to microwave integrated circuits. ABSTRACT | In modern wireless communication systems, it is very important to realize simultaneously high-efficiency and linear operation of power amplifiers. This paper-overview describes the historical aspect of the Doherty approach to the power-amplifier design introduced in 1936 and modern trends in Doherty amplifier (DA) design techniques using multistage and asymmetric multiway architectures. To increase efficiency over the power backoff range, the switchmode class-E, conventional class-F, or inverse class-F operation mode by controlling the second and third harmonics can be used in the load network. The DA with a series-connected load, and inverted, pushpull, balanced, and parallel Doherty architectures are also described and discussed. Finally, examples of the lumped DA implemented in monolithic microwave integrated circuits, digitally driven Doherty technique, and broadband capability of the two-stage DA are given.
Toward a More Generalized Doherty Power Amplifier Design for Broadband Operation
IEEE Transactions on Microwave Theory and Techniques, 2016
The conventional Doherty power amplifier (DPA) theory is limited to single carrier operations, leading to a nongeneric structure. This paper presents a new analysis that generalizes the conventional DPA theory for increased efficiency and bandwidth. We demonstrate that by introducing a theoretical parameter ߙ at the output combiner we can redefine the relationships among the output combiner elements for a greater level of design flexibility than it was possible in the conventional DPA. We also show that previously published works in this area can be considered as special cases of the proposed general theory. As a demonstrator, a specific design, named Reduced-ࢻ Doherty power amplifier, realized using GaN HEMTs is provided to illustrate the robustness of the approach. This design proves effective for further improving the performance of the previously published 2.14/2.655 GHz dual-band parallel DPA. A maximum drain efficiency of 84% and 67% at an average of 43-dBm peak and 6-dB back-off power levels, respectively, were measured with continuous wave signals. To quantify the linearity performance, the proposed DPA was tested using wideband CDMA and longterm evolution (LTE) signals where the adjacent channel leakage ratio was recorded at-25 dBc with an average output power of 38.7 and 36.5 dBm at 2.14 and 2.655 GHz, respectively.
Doherty amplifier with DSP control to improve performance in CDMA operation
2003
A power amplifier for CDMA applications which consists of a Doherty amplifier and a digital signal processing (DSP) controller is presented. DSP is used to dynamically adjust the gate bias of the auxiliary (peaking) amplifier at the rate of the signal envelope to obtain gain flatness (i.e. AM-AM distortion correction). Furthermore, DSP is used as a digital predistortor to improve the overall linearity by adjusting the phase at baseband (i.e. AM-PM distortion correction). The 840MHz Doherty amplifier is realized with two commercially available MESFETs in a hybrid circuit, and the DSP is implemented externally with a board controlled by a personal computer. It is shown that by utilizing these DSP techniques, the overall linearity and efficiency characteristics of the Doherty amplifier can be significantly improved.
The Doherty Power Amplifier: Review of Recent Solutions and Trends
IEEE Transactions on Microwave Theory and Techniques, 2015
In this work, an extensive review of the most up-todate papers on microwave Doherty power amplifiers is presented. The main applications are discussed, together with the employed semiconductor technologies. The different research trends, all aimed to improve the advantages of the Doherty scheme and to solve its inherent drawbacks, are presented. The first considered topic is the maximization of efficiency and/or linearity, where analog and digital techniques are exploited. Another important trend is the bandwidth enlargement of the Doherty architecture, that involves a large number of papers. Multi-band, multi-mode solutions are also considered, using either fixed or reconfigurable solutions. The final section is dedicated to the most significant Doherty integrated implementation.