Electronic Interconnect � Printed Circuit Board � Manufacturing � (original) (raw)
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On the Electromagnetic Radiation of Printed-Circuit-Board Interconnections
IEEE Transactions on Electromagnetic Compatibility, 2005
Large ground and supply layers on interconnected boards represent a radiating antenna structure which may be efficiently excited at its resonances by small high-frequency potential differences. Such potential differences between the boards mainly originate from the inevitable inductive impedance of the signal-current return path in the connector, usually provided by ground pins. The presented modeling approach is based on an antenna transfer function for the global interconnecting structure and a partial-inductance equivalent circuit for the connector. As shown by the example of a motherboard-daughterboard structure, the model enables a systematic study of the radiation mechanism, depending on signal/ground-pin configuration, as well as geometrical and electrical parameters. In conjunction with SPICE simulations of the connector equivalent circuit, the signal driver and receiver dynamic characteristic can also be properly included. Validation is provided by full-wave simulation and measurement results.
2003
Introduction Thin layers (50 um) of FR-4 material have been used for power-ground cores for a number of years to improve electrical performance. These thin power-ground cores serve as distributed capacitor layers to assist in power supply decoupling. However, with the ever-increasing speeds of circuits and the trend to lower voltages and higher switching speeds, these thin layers no longer provide the required electrical properties (low impedance, high capacitance) necessary for next generation, high speed digital circuits. New ultra-thin (<25 um) dielectric materials loaded with high dielectric constant materials have been developed to meet the low target impedance values and high capacitance necessary for effective power supply decoupling for these next generation products. Sun Microsystems designed a multilayer printed circuit board that was used to measure self and transfer-impedance values over a wide frequency range. Test boards were fabricated and electrically tested with ...
Electric pulse induced impedance and material degradation in IC chip packaging
A method for measurement of electric circuit conduction path by Scan Electron Microscopy (SEM) has been developed. It shows that current conducts through the whole surface layer of solder joints when subjected to high frequency pulse loadings, but only half of the surface layer when subjected to AC loading. The Electrical Pulse Induced Resistance Change (EPIR) profile of a symmetric solder bump thin film structure of a typical IC chips packaging is studied. EPIR is found to be frequency, duty factor and current density dependent. An average current density model is proposed to approximate duty factor and the current density induced EPIR effects.
Evaluation of the Radiated Emission of a Printed Circuit Board Attached with Cables
Proceedings of the 3rd International Conference on Electric and Electronics, 2013
An electronic product has to comply with a myriad of EMC requirements before it can be marketed globally. Radiated Emission is one of the EMC requirements which constantly poses a challenge to many circuit designer due to the ever increasing speed of PCB clocks. Consequently, in the product it is essential to investigate, identify, model and predict the PCB radiated emission before compliance test is performed for cost and time saving. In this paper, a simple double layer PCB board is fabricated to investigate the PCB radiated emission. Three PCB configurations are investigated for the level of emissions and to correlate with the common-mode currents. These configurations are PCB without attached cables, with one attached cable and with two attached cables. The radiated emission from each configuration is measured in a semi-anechoic chamber at open circuit and 50 ohm loads. It can be shown that the cables are the major sources of radiated emission due to the common-mode currents flowing through it.
2010 IEEE International Symposium on Electromagnetic Compatibility, 2010
This paper investigates the impact of return path discontinuities on both signal and power integrity of high speed interconnects. A test board is built for the purpose and 4 different configurations are analyzed and correlation between measurements and simulations (coming from a full wave 3D EM field simulator) results is also presented. Both time and frequency domain results are analyzed and design guidelines are provided. It is observed that return path discontinuities have a sensible impact on ground bounce in single-ended signals; however the differential signaling can drastically reduces it. Discontinuities from gaps in return paths (e.g. plane splits) and connectors impact the differential signals on both insertion loss and cross talk. The real value of return/grounding vias is to reduce the common signal noise.
Parasitic modes on printed circuit boards and their effects on EMC and signal integrity
IEEE Transactions on Electromagnetic Compatibility, 2001
In this paper, parasitic modes, such as slotline, parallel plane, and surface wave (SW) modes, commonly found on printed circuit boards (PCBs) will be analyzed and their effects on electromagnetic compatibility (EMC) and signal integrity will be discussed. The analysis is based on numerical simulations using the finite difference time domain (FDTD) method which will be shown to be very well suited for rigorous modeling of parasitic mode effects. EMC and signal integrity problems discussed include power loss, crosstalk, ground bounce, and free space radiation. Design guidelines for improved EMC and signal integrity are derived from the results obtained. Comprehensive simulation and characterization of SWs using FDTD is presented for the first time.
MRS Proceedings, 1984
Etched metallic conductor lines on metal clad polymeric substrates are used for electronic component interconnections. Significant signal losses are observed for microstrip conductor lines used for interconnecting high Frequency (above 20 GHz) devices. At these frequencies, the electronic signal travels closer to the metal-polymer interface due to the skin effect. Copper-teflon interfaces were characterized by SEM and AES to determine the interfacial properties. Data relating roughness of the copper film to signal losses was compared to theory. Films used to enhance adhesion, were also found, to a lesser extent, to contribute to these losses.
Analysis of Electromagnetic Interference Reduction from Printed Circuit Boards
Highlights in Science, Engineering and Technology
Nowadays, electricity is the most important and necessary energy in human society and daily life, because electricity is convenient and safe to transfer between different locations. However, electromagnetic interference (EMI) always accompanies electricity and has brought a lot of problems. Especially in printed circuit boards (PCB), the EMI can break the circuit or cause a short circuit, which is dangerous in creating a PCB. To effectively reduce EMI from PCB, three different methods of reducing EMI from PCB were chosen to compare with each other. By comparing their price, practicability, effectiveness, data, and technology for reducing EMI from PCB, PCB designers can choose the methods that are suitable for their situation.
IEEE Transactions on Electromagnetic Compatibility, 2000
A comprehensive overview is given of the strengths, limitations, and applicability of the short-pulse propagation technique (SPP). SPP is shown to be able to extract the broadband characteristics of a wide range of interconnect technologies found in digital computer applications and generate causal predictive models. Examples are given of such applications from on-chip wiring, ceramic and organic chip carrier, cards, boards, to cables, and structures with large inhomogeneities, such as found in differential and microstrip cases, irregularities (such as introduced by roughening of metallization), and various operating conditions, such as variable temperature and humidity. The use of SPP as a virtual test bench is explained and showcased through the analysis of the impact of manufacturing tolerances and via stub length on the electrical characteristics. The diverse versatility of the SPP method is discussed through many examples on practical interconnect structures with special emphasis on printed circuit board wiring.