Morphology and Current–Voltage Characteristics of Nanostructured Pentacene Thin Films Probed by Atomic Force Microscopy (original) (raw)
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ACS Applied Materials & Interfaces, 2010
Field-effect mobility (µ) of pentacene-based organic field-effect transistors (OFETs) is studied as a function of the number of molecular monolayer (ML) by in situ electrical characterization, which greatly improves the accuracy and reproducibility of electrical characteristics of OFETs. The hole µ of pentacene OFET with an average 1 ML (∼1.57 nm) thickness has been observed under a vacuum. The µ of pentacene OFET rapidly increases with increasing surface coverage in the region of film thickness less than saturation thickness (d 0 ), which is about 3.2 ML for pentacene OFETs studied herein. We have observed that pentacene molecular layers beyond d 0 have little contribution to the carrier transport in the semiconducting channel. The threshold voltage (V T ) of pentacene OFETs has a variable thickness dependence having minimum ∼17 V at pentacene thickness around 3.2 ML. Similar d 0 was verified for both drain current and on/off current ratio of pentacene FETs. The atomic force microscopy (AFM) images of the pentacene layer confirm the layer-plus-island (Stranski-Krastanov mode) pentacene growth mechanism on SiO 2 substrate. Terrace-like stacking structure begins to be disernable around 3.2 ML of pentacene thin film. From AFM images, top few layers of pentacene terrace stacking become smaller in size after reaching the largest domain size around 10 ML. Our experimental results have demonstrated that the growth quality of the first few pentacene MLs on substrate strongly influences the morphology of the thicker film, packing structure, and electrical characteristics of OFET, including change-carrier mobility. FIGURE 7. AFM images (5 × 5 µm 2 ) of the surface of pentacene thin film (on SiO 2 substrates) with various thickness ranging from 0.3 to 100 MLs. ARTICLE www.acsami.org
Applied Physics Letters, 2008
Oriented pentacene nanocrystals with long molecular axis either parallel or perpendicular to a Au substrate were prepared on a bare Au surface or a self-assembled monolayer ͑SAM͒-modified Au surface, respectively. The conductance across the differently oriented pentacene crystals were measured by conductive atomic force microscopy in a similar device configuration of Au/SAM/ pentacene/Au-tip and Au/pentacene/SAM-modified-Au-tip, respectively. Rectifying current was observed depending on the location of the SAM in the device. With an average thickness of 50 nm, the conductance along the C-H¯ stacking direction ͑a-b plane͒ was nearly five orders of magnitude larger than along the layer direction ͑c axis͒.
Charge transport and morphology of pentacene films confined in nano-patterned region
NPG Asia Materials, 2014
The transport and morphology of macroscopic organic transistors have been thoroughly explained. However, the relationship between charge transport and the morphology of organic semiconductors in nano-confined regions is not well understood, which is required to design high-performance nano-electronics. Therefore, in this study, the electrical performance of pentacene thin-film transistors (TFTs) fabricated on nano-scale confined geometries was compared with that of other TFT systems fabricated on micro-scale confined or flat dielectrics. The results showed that the photoresist (PR) reliefs patterned onto silicon dioxide (SiO 2) dielectrics could control the growth mode of pentacene in the confined regions. As the line spacing between the PR patterns decreased to below the average size of pentacene normally grown on SiO 2 dielectrics (B1.7 lm), field-effect mobility (l FET) of pentacene TFTs improved considerably. Specifically, the l FET values for the 250 nm patterned dielectric system were as high as 0.33 cm 2 V À1 s À1 , which was greater than those of the wider-patterned PR or flat dielectric systems (p 0.15 cm 2 V À1 s À1). These findings were related to the enhancement of charge-carrier transport owing to the anisotropic p-conjugated crystals nucleated from the nano-confined edges, providing important information that can be used in the design of high-performance nano-scale organic electronics.
2004
We have fabricated pentacene-based thin film transistors and analyzed their electrical properties with the help of two-dimensional drift-diffusion simulations which favorably compare with the experimental results. We have set up a model considering the polycrystalline nature of pentacene and the presence of grains and grain boundaries. We show how this model can be applied to different devices with different grain sizes and we analyze the relationship between mobility, grain size and applied gate voltage. On the basis of the simulation results, we can introduce an effective carrier mobility, which accounts for grain-related effects. The comparison between experimental results and simulations allows us to clearly understand the differences in the mobility derived by the analysis of current-voltage curve (as done experimentally by using standard MOSFET theory) and the intrinsic mobility of the organic layer. The effect of the pentacene/oxide interface traps and fixed surface charges has also been considered. The dependence of the threshold voltage on the density and energy level of the trap states has been outlined.
Effect of impurities on pentacene thin film growth for field-effect transistors
2008
Pentacenequinone (PnQ) impurities have been introduced into a pentacene source material at number densities from 0.001 to 0.474 to quantify the relative effects of impurity content and grain boundary structure on transport in pentacene thin-film transistors. Atomic force microscopy (AFM) and electrical measurements of top-contact pentacene thin-film transistors have been employed to directly correlate initial structure and final film structures, with the device mobility as a function of added impurity content. The results reveal a factor four decrease in mobility without significant changes in film morphology for source PnQ number fractions below ~0.008. For these low concentrations, the impurity thus directly influences transport, either as homogeneously distributed defects or by concentration at the otherwise-unchanged grain boundaries. For larger impurity concentrations, the continuing strong decrease in mobility is correlated with decreasing grain size, indicating an impurity-induced increase in the nucleation of grains during early stages of film growth.
Imaging of Crystal Morphology and Molecular Simulations of Surface Energies in Pentacene Thin Films
The Journal of Physical Chemistry B, 2006
We have investigated the crystal growth of the organic semiconductor pentacene by complementing molecular simulations of surface energies with experimental images of pentacene films. Pentacene thin films having variations in thickness and grain size were produced by vacuum sublimation. Large (∼20 µm) faceted crystals grew on top of the underlying polycrystalline thin film. The films were characterized using optical microscopy (OM), X-ray diffraction (XRD), scanning electron microscopy (SEM), and transmission electron microscopy (TEM). Single crystals most commonly grew in a truncated diamond shape with the largest crystal face, (001), growing parallel to the substrate. Crystal morphologies and surface energies were calculated using force field-based molecular simulations. The (001) surface was found to have the lowest energy, at 76 mJ/ m 2 , which was consistent with experimental observations of crystal face size. It was demonstrated that the morphology of the large faceted crystals approached the equilibrium growth shape of pentacene. From contact angle measurements, the critical surface tension of textured pentacene thin films in air was determined to be 34 mJ/m 2 .
IEEE Transactions on Electron Devices, 2018
The impact of electrodes and active layer thickness on the current-voltage characteristics of Au/Pentacene/Al structure was studied using a physicallybased 2-D simulation by solving Poisson's, continuity, and drift diffusion equations. The main parameters required for simulation are extracted from the logarithmic representation of experimental current-voltage curves. The simulation results produce an excellent overlapping with the experimental data after including parameters previously found in our model. Finally, the simulation was used to better understand the physical processes together with mechanisms governing the efficiency of the device under investigation and to have a predictive behavior.
Organic Electronics, 2015
In this work we present in situ electrical and surface analytical, as well as ex situ atomic force microscopy (AFM) studies on temperature and surface condition induced pentacene layer growth modifications, leading to the selection of optimized deposition conditions and entailing performance improvements. We prepared p ++-silicon/silicon dioxide bottom-gate, gold bottomcontact transistor samples and evaluated the pentacene layer growth for three different surface conditions (sputtered, sputtered + carbon and unsputtered + carbon) at sample temperatures during deposition of 200 K, 300 K and 350 K. The AFM investigations focused on the gold contacts, the silicon dioxide channel region and the highly critical transition area. Evaluations of coverage dependent saturation mobilities, threshold voltages and corresponding AFM analysis were able to confirm that the first 3-4 full monolayers contribute to the majority of charge transport within the channel region. At high temperatures and on sputtered surfaces uniform layer formation in the contact-channel transition area is limited by dewetting, leading to the formation of trenches and the partial development of double layer islands within the channel region instead of full wetting layers. By combining the advantages of an initial high temperature deposition (well-ordered islands in the channel) and a subsequent low temperature deposition (continuous film formation for low contact resistance) we were able to prepare very thin (8 ML) pentacene transistors of comparably high mobility.