Growth of nanowire arrays from micron-feature templates (original) (raw)
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High yield of GaAs nanowire arrays on Si mediated by the pinning and contact angle of Ga
Nano letters, 2015
GaAs nanowire arrays on silicon offer great perspectives in the optoelectronics and solar cell industry. To fulfil this potential, gold-free growth in predetermined positions should be achieved. Ga-assisted growth of GaAs nanowires in the form of array has been shown to be challenging and difficult to reproduce. In this work we provide some of the key elements for obtaining a high yield of GaAs nanowires on patterned Si in a reproducible way: contact angle and pinning of the Ga droplet inside the apertures achieved by the modification of the surface properties of the nanoscale areas exposed to growth. As an example, an amorphous silicon layer between the crystalline substrate and the oxide mask results in a contact angle around 90o, leading to a high yield of vertical nanowires. Another example for tuning the contact angle is anticipated, native oxide with controlled thickness. This work opens new perspectives for the rational and reproducible growth of GaAs nanowire arrays on silicon.
Generic nano-imprint process for fabrication of nanowire arrays
Nanotechnology, 2010
A generic process has been developed to grow nearly defect free arrays of (heterostructured) InP and GaP nanowires. Soft nanoimprint lithography has been used to pattern gold particle arrays on full 2 inch substrates. After lift-off organic residues remain on the surface, which induce the growth of additional undesired nanowires. We show that cleaning of the samples before growth with piranha solution in combination with a thermal anneal at 550 °C for InP and 700 °C for GaP results in uniform nanowire arrays with 1% variation in nanowire length, and without undesired extra nanowires. Our chemical cleaning procedure is applicable to other lithographic techniques such as e-beam lithography, and therefore represents a generic process.
Position-Controlled Uniform GaAs Nanowires on Silicon using Nanoimprint Lithography
Nano Letters, 2014
We report on the epitaxial growth of large-area position-controlled self-catalyzed GaAs nanowires (NWs) directly on Si by molecular beam epitaxy (MBE). Nanohole patterns are defined in a SiO 2 mask on 2 in. Si wafers using nanoimprint lithography (NIL) for the growth of positioned GaAs NWs. To optimize the yield of vertical NWs the MBE growth parameter space is tuned, including Ga predeposition time, Ga and As fluxes, growth temperature, and annealing treatment prior to NW growth. In addition, a non-negligible radial growth is observed with increasing growth time and is found to be independent of the As species (i.e., As 2 or As 4 ) and the growth temperatures studied. Cross-sectional transmission electron microscopy analysis of the GaAs NW/Si substrate heterointerface reveals an epitaxial growth where NW base fills the oxide hole opening and eventually extends over the oxide mask. These findings have important implications for NW-based device designs with axial and radial p−n junctions. Finally, NIL positioned GaAs/AlGaAs core−shell heterostructured NWs are grown on Si to study the optical properties of the NWs. Room-temperature photoluminescence spectroscopy of ensembles of as-grown core−shell NWs reveals uniform and high optical quality, as required for the subsequent device applications. The combination of NIL and MBE thereby demonstrates the successful heterogeneous integration of highly uniform GaAs NWs on Si, important for fabricating high throughput, large-area position-controlled NW arrays for various optoelectronic device applications.
Nano Letters, 2008
We report the controlled growth of planar GaAs semiconductor nanowires on (100) GaAs substrates using atmospheric pressure metalorganic chemical vapor deposition with Au as catalyst. These nanowires with uniform diameters are self-aligned in <110> direction in the plane of (100). The dependence of planar nanowire morphology and growth rate as a function of growth temperature provides insights into the growth mechanism and identified an ideal growth window of 470 (10°C for the formation of such planar geometry. Transmission electron microscopy images reveal clear epitaxial relationship with the substrate along the nanowire axial direction, and the reduction of twinning defect density by about 3 orders of magnitude compared to <111> III-V semiconductor nanowires. In addition, using the concept of sacrificial layers and elevation of Au catalyst modulated by growth condition, we demonstrate for the first time a large area direct transfer process for nanowires formed by a bottom-up approach that can maintain both the position and alignment. The planar geometry and extremely low level of crystal imperfection along with the transferability could potentially lead to highly integrated III-V nanoelectronic and nanophotonic devices on silicon and flexible substrates.
Nanotechnology, 2012
We report a non-lithographical method for the fabrication of ultra-thin silicon (Si) nanowire (NW) and nano-sheet arrays through metal-assisted-chemical-etching (MacEtch) with gold (Au). The mask used for metal patterning is a vertical InAs NW array grown on a Si substrate via catalyst-free, strain-induced, one-dimensional heteroepitaxy. Depending on the Au evaporation angle, the shape and size of the InAs NWs are transferred to Si by Au-MacEtch as is (NWs) or in its projection (nano-sheets). The Si NWs formed have diameters in the range of ∼25-95 nm, and aspect ratios as high as 250 in only 5 min etch time. The formation process is entirely free of organic chemicals, ensuring pristine Au-Si interfaces, which is one of the most critical requirements for high yield and reproducible MacEtch.
Circuit Fabrication at 17 nm Half-Pitch by Nanoimprint Lithography
Nano Letters, 2006
High density metal cross bars at 17 nm half-pitch were fabricated by nanoimprint lithography. Utilizing the superlattice nanowire pattern transfer technique, a 300-layer GaAs/AlGaAs superlattice was employed to produce an array of 150 Si nanowires (15 nm wide at 34 nm pitch) as an imprinting mold. A successful reproduction of the Si nanowire pattern was demonstrated. Furthermore, a cross-bar platinum nanowire array with a cell density of approximately 100 Gbit/cm 2 was fabricated by two consecutive imprinting processes.
Physica E: Low-dimensional Systems and Nanostructures, 2005
We have demonstrated a new planar edge defined alternate layer (PEDAL) process to make sub-25 nm nanowires across the whole wafer. The PEDAL process is useful in the fabrication of metal nanowires directly onto the wafer by shadow metallization and has the ability to fabricate sub-10 nm nanowires with 20 nm pitch. The process can also be used to make templates for the nano-imprinting with which the crossbar structures can be fabricated. The process involves defining the edge by etching a trench patterned by conventional i-line lithography, followed by deposition of alternating layers of silicon nitride and crystallized a-Si. The thickness of these layers determines the width and spacing of the nanowires. Later the stack is planarized to the edge of the trench by spinning polymer Shipley 1813 and then dry etching the polymer, nitride and polysilicon stack with non-selective RIE etch recipe. Selective wet etch of either nitride or polysilicon gives us the array of an aligned nanowires template. After shadow metallization of the required metal, we get metal nanowires on the wafer. The process has the flexibility of routing the nanowires around the logic and memory modules all across the wafer. The fabrication facilities required for the process are readily available and this process provides the great alternative to existing slow and/or costly nanowire patterning techniques.
Tailoring the diameter and density of self-catalyzed GaAs nanowires on silicon
Nanotechnology, 2015
Nanowire diameter has a dramatic effect on the absorption cross-section in the optical domain. The maximum absorption is reached for ideal nanowire morphology within a solar cell device. As a consequence, understanding how to tailor the nanowire diameter and density is extremely important for high-efficient nanowire-based solar cells. In this work, we investigate mastering the diameter and density of self-catalyzed GaAs nanowires on Si(111) substrates by growth conditions using the self-assembly of Ga droplets. We introduce a new paradigm of the characteristic nucleation time controlled by group III flux and temperature that determine diameter and length distributions of GaAs nanowires. This insight into the growth mechanism is then used to grow nanowire forests with a completely tailored diameter-density distribution. We also show how the reflectivity of nanowire arrays can be minimized in this way. In general, this work opens new possibilities for the cost-effective and controlled...
2014
Many techniques have been applied to fabricate nanostructures via top-down approach such as electron beam lithography. However, most of the techniques are very complicated and involves many process steps, high cost operation as well as the use of hazardous chemicals. Meanwhile, atomic force microscopy (AFM) lithography is a simple technique which is considered maskless and involves only an average cost and less complexity. In AFM lithography, the movement of a probe tip can be controlled to create nanoscale patterns on sample surface. For silicon nanowire (SiNW) fabrication, a conductive tip was operated in non-contact AFM mode to grow nanoscale oxide patterns on silicon-on-insulator (SOI) wafer surface based on local anodic oxidation (LAO) mechanism. The patterned structure was etched through two steps of wet etching processes. First, the TMAH was used as the etchant solution for Si removing. In the second step, diluted HF was used to remove oxide mask in order to produce a completed SiNW based devices. A SiNW based device which is formed by a nanowire channel, source and drain pads with lateral gate structures can be fabricated by well controlling the lithography process (applied tip voltage and writing speed) as well as the etching processes.