Implementation of Multiplier Using Vedic Mathematics (original) (raw)

Design and Implementation of High Speed Multiplier based on Vedic Mathematics: A Review

International Journal of Computer Applications, 2016

Multipliers being the key components of various applications and the throughput of applications depends on Arithmetic and logic units(ALU), Digital signal processing blocks and Multiplier and accumulate units. Vedic Multiplier has become highly popular as a faster method for computation and analysis.So that the latency of conventional multiplier can be reduced. Here the vedic mathematic Sutra-'Urdhva Tiryagbhyam' and Nikhilum are used for efficient multiplication. The main parameters for improvement are speed, delay, hardware complexity. From this review, the conclusion regarding how well a challenge has been solved, and recognize prospective research areas that require auxiliary effort.

Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques

This paper proposed the design of high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that have been modified to improve performance. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. The work has proved the efficiency of Urdhva Triyagbhyam-Vedic method for multiplication which strikes a difference in the actual process of multiplication itself. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros and scaled to higher bit levels using Karatsuba algorithm with the compatibility to different data types. Urdhva tiryakbhyam Sutra is most efficient Sutra (Algorithm), giving minimum delay for multiplication of all types of numbers, either small or large. Further, the Verilog HDL coding of Urdhva tiryakbhyam Sutra for 32x32 bits multiplication and their FPGA implementation by Xilinx Synthesis Tool on Spartan 3E kit have been done and output has been displayed on LCD of Spartan 3E kit. The synthesis results show that the computation time for calculating the product of 32x32 bits is 31.526 ns.

IMPLEMENTATION OF MULTIPLICATION ALGORITHM USING VEDIC MULTIPLICATION: A REVIEW

At present, it has been necessary to increase the speed of multiplier as the need of high speed processors is increasing. Multiplier is an important basic function in most fast processing system. Conventional processors need great hardware resources and take more time in multiplication operation. This paper presents high speed multiplier depending on vertical & crosswise method of Vedic mathematics. Implementation is carried on digital hardware. Vedic multiplication needs same number of addition and multiplication operations of normal multiplier using digital hardware; wherein mental calculation is the only case where it differs. Few VHDL codes have been programmed for the same. An efficient implementation of high speed multiplier using the Vedic multiplication method. In this we compare the working of the three multiplier by implementing each of them on FPGA Spartan3 board. As far as comparison is concerned, all multipliers have been tested for 8, 16 and 32 bits multiplications. In our project when we compare the path delay of all the multipliers we find that 8 bit and 16bit Urdhva algorithm gives 50% better delay than that of Nikhilam whereas 100% than that of Binary multiplier.. The result of work helps us to choose a better option between methods of vedic multiplier in fabricating different systems. Multipliers form one of the most important component of many systems. So by analyzing the working of different multipliers helps to frame a better system with less path delay.

High Speed Multiplier based on Ancient Indian Vedic Mathematics

2015

Multiplier is one of the key hardware component in high performance system such as Finite Impulse Response (FIR) filters and Digital Signal Processor (DSP). Multiplier consumes large chip area, long latency and consume considerable amount of power. Hence better multiplier architectures can increase the efficiency of the system. Multiplier based on Vedic mathematics is one such promising solution. For the multiplication, Urdhva Tiryagbhyam sutra and Nikhilam sutra is used from Vedic mathematics. The paper shows the design implementation and comparison of these multiplier using Verilog Hardware Description Language (HDL). The multiplier based on Urdhva Tiryagbhyam sutra reduces the execution time by maximum 58% and minimum 9% but Multiplier based on Nikhilam sutra reduces the execution time by minimum 13% compared to array multiplier and increases 87% compared to Wallace tree multiplier.

Design of Efficient High Speed Vedic Multiplier

IJSRD, 2013

Multipliers are extensively used in Microprocessors, DSP and Communication applications. For higher order multiplications, a huge number of adders are to be used to perform the partial product addition. This paper proposed the design of high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that have been modified to improve performance. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. The work has proved the efficiency of Urdhva Triyagbhyam. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps. Urdhva tiryakbhyam Sutra is most efficient Sutra (Algorithm), giving minimum delay for multiplication of all types of numbers, either small or large.

Designing Of Fast Multipliers with Ancient Vedic Techniques

Vedic mathematics is an ancient system of mathematics which performs unique technique of calculations based on 16 sutras. The performance of high speed multiplier is designed based on Urdhva Tiryabhyam, Nikhilam Navatashcaramam Dashatah, and Anurupye algorithms. These algorithms gives minimum delay and used for multiplication of all types of numbers. The performance of high speed multiplier is designed and compared using these sutras for various NxN bit multiplications and implemented on the FFT of the DSP processor. Anurupye Vedic multiplier on FFT is made efficient than Urdhva tiryabhyam and Nikhilam Navatashcaramam Dashatah sutras by more reduction in computation time. Logic verification of these design is verified by simulating the logic circuits in XILINX ISE 9.1 and MODELSIM SE 5.7g using VHDL.

Design And Implementation Of High Speed Vedic Multiplier

Vedic mathematics is the ancient Indian system of mathematics. This paper proposed the design oh high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that has been modified to improve performance. Multipliers play a major role in processors and in many computational systems. The speed of these systems greatly depends on the speed of its multipliers. In order to enhance the speed of the systems the faster and efficient multipliers should be employed. Vedic Multiplier is one of the best solution which is capable of performing the quicker multiplications by eliminating the unwanted steps in the multiplication process. Vedic Multiplier deals with a total of sixteen sutras or algorithms for predominantly logical operations. In this paper it is used for designing a high speed, low power 4X4 multiplier. In the proposed design we have reduced the number of logic levels, thus reducing the logic delay. The proposed system is design using VHDL and it is implemented through Xilinx 8.1.

Implementation of an Efficient Multiplier based on Vedic Mathematics Using High speed adder

2014

A high speed controller or processor depends vastly on the multiplier as it is one of the main hardware blocks in most digital signal processing unit as well as in general processors. This paper presents a high speed Vedic multiplier architecture which is quite different from the Conventional Vedic multiplier. The most significant aspect of the proposed method is that, the developed multiplier architecture uses Carry look ahead adder as a key block for fast addition. Using Carry look ahead adder the performance of multiplier is vastly improved. This also gives chances to break whole design into smaller blocks and use it whenever required. So by using structural modeling we can easily make large design by using small design and thus complexity gets reduced for inputs of larger no of bits. We had written code for proposed new Vedic multiplier using VHDL (Very High Speed Integrated Circuits Hardware Description Language), synthesized and simulated using XilinxISE8.1i and downloaded to ...

HIGH SPEED MULTIPLIER USING VEDIC MATHEMATICS

The digital signal processing in today's time need high speed computation. The basic building block of signal processing in Communication, Biomedical signal processing, and Image processing remains Fast Fourier Transform (FFT). FFT computation involves multiplications and additions. Speed of the DSP processor mainly depends on the speed of the multiplier. Time delay, power dissipation and the silicon chip area. These are the most important parameters for the fast growing technology. The conventional multiplication method requires more time and area and hence more power dissipation. In this paper an ancient Vedic multiplication method called "Urdhva Triyakbhyam" is implemented. It is a method based on 16 sutras of Vedic mathematics. Vedic Mathematics reduces the number of operations to be carried out compared to the conventional method. The code description is simulated and synthesized using FPGA device Spartan XC3S400-PQ208.

An Efficient High-Performance Vedic Multiplier: Review

INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING AND MANAGEMENT

Multipliers are the most essential block of any processor. Multiplication is one of the important operations in digital signal processors. The processing speed of a ALU is depends on its logic algorithm and complexity of hardware circuitry delay. Basically delay is depending on number of bits increases. For efficient processors, delay should minimum; to minimize delay optimized hardware architecture for process is required. Vedic Multipliers are able to deal with the above credential of minimum hardware architecture. In this review a comprehensive analysis of binary multiplication algorithm and Vedic multiplication algorithm has presented.