A Retargetable Tool-Suite for the Design of Application Specific Instruction Set Processors Using a Machine Description Language (original) (raw)

APDL: A Processor Description Language For Design Space Exploration of Embedded Processors

Forum on specification & Design Languages, 2007

Abstract—This paper presents Anahita Processor Description Language (APDL) for generation of retargetable processor de- sign tool sets. The emphasis,is onthe applicability of the gener- ated tools in the ,design space exploration (DSE) phase of de- signing a new,embedded,processor. APDL descriptions can be used for generating cycle-accurate instruction set simulators, assembler/disassembler tools, production quality compilers and architecture verification tools. The paper

Automated processor generation for system-on-chip

Proceedings of the 27th European Solid-State Circuits Conference, 2001

New application-focused system-on-chip platforms motivate new application-specific processors. Configurable and extensible processor architectures offer the efficiency of tuned logic solutions with the flexibility of standard high-level programming methodology. Automated extension of processor function units and the associated software environment - compilers, debuggers, simulators and real-time operating systems - satisfies these needs. At the same time, designing at the level of software and instruction set architecture significantly shortens the design cycle and reduces verification effort and risk. This paper describes the key dimensions of extensibility within the processor architecture, the instruction set extension description language and the means of automatically extending the software environment from that description. It also describes two groups of benchmarks, EEMBC's Consumer and Telecommunications suites, that show 20 to 40 times acceleration of a broad set of alg...

Retargetable compiled simulation of embedded processors using a machine description language

ACM Transactions on Design Automation of Electronic Systems, 2000

Fast processor simulators are needed for the software development of embedded processors, for HW/SW cosimulation systems, and for profiling and design of application-specific processors. Such fast simulators can be generated based on the machine description language LISA. Using this language to model processor architectures enables the generation of compiled simulators on various abstraction levels, assemblers, and compiler back ends. The article discusses the requirements of software development tools on processor models and presents the approach based on the LISA language. Furthermore, the implementation of a retargetable environment consisting of compiled simulator, debugger, and assembler is presented. Measurements for a verified, cycle-based LISA model of the TI TMS320C62× DSP show that that this approach achieves between 37× and 170× higher simulation speed compared to a commercial simulator using a standard technique and the same accuracy level.

An architecture synthesis system for embedded processors

2000

Design requirements for embedded systems call for architectures with small size, low power consumption and low cost. These requirements can be met by designing custom architectures for every single application. However, the commercial viability of embedded systems calls for short design cycles. These requirements are conflicting: custom architectures take a long time and substantial effort to produce, because of the need to manually generate design evaluation tools, such as simulators and compilers, for each architecture candidate. This conflict can be eliminated by providing a system capable of generating all design evaluation tools for a given candidate architecture. This thesis presents two components of the ARIES environment for architecture synthesis: the machine description language ISDL and the G ENSIM simulator generator system. We also briefly describe the H GEN hardware model generator. In the ARIES system, candidate architectures are described in the ISDL language. From t...