Very Low-Voltage Digital-Audio Delta-Sigma Modulator with 88-dB Dynamic Range Using Local Switch Bootstrapping (original) (raw)
Related papers
Sigma-Delta Modulator Design and Analysis for Audio Application
International Journal of Engineering Trends and Technology, 2015
A Sigma-delta modulator is designed in 180nm CMOS process for digital Audio applications. This design is simulated on S-Edit of Tanner EDA tool. In this design continuous time sigma-delta modulator is implemented to reduce the noise problem. This sigma-delta modulator also helps to reduce power consumption of circuit. In these design two stage op-amps is used to implement modulator. Also this design uses second order continuous time modulator for increasing SNR. Circuit design an 11bit low power sigma-delta modulator for digital audio application is given, using a single bit quantizer. The power supply for this circuit is only 1.8v; the modulator achieves 72dB SNR in a 20 KHz BW, while consuming 1mW.
2010
The design of a single-loop 4 th order 10MHz bandwidth, 320MHz sampling frequency (OSR=16) continuous-time delta-sigma is presented. This design is intended to minimize the power consumption in a low-voltage environment. A low power, low noise complimentary input OPAMP, the most power-consumed block in the modulator, is proposed in this design. As a result, the modulator achieves a simulated peak SNDR of 77dB in a 10MHz bandwidth, consumes 8.1mW at 1.2V supply voltage, and occupies an area of 900μm x 480μm in a standard 90nm CMOS process.
A 1.5-V-100-μW ΔΣ modulator with 12-b dynamic range using the switched-opamp technique
IEEE Journal of Solid-State Circuits, 1997
The design and implementation of a very low supply voltage/low power 16 modulator is presented. It is based on the switched-opamp technique, which allows low voltage operation with a standard process and without voltage multiplication. The design methodology is illustrated with a second-order single-loop 16 modulator. The chip is implemented in a 0.7-m CMOS process with standard threshold voltages. The power supply is 1.5 V and the power dissipation is only 100 W. The measured dynamic range in the speech bandwidth of 300-3400 Hz is 12 b.
A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC
IEEE Journal of Solid-State Circuits, 2000
A 0.5-V third-order one-bit fully-differential continuous-time 16 modulator is presented. The presented modulator architecture uses true low-voltage design techniques, and does not require internal voltage boosting or low-threshold devices. A return-to-open architecture that enables the ultra-low-voltage realization of return-to-zero signaling for the feedback DAC is proposed. The ultra-low-voltage operation is further enabled by a body-input gate-clocked comparator, and body-input operational transconductance amplifiers for the active-RC loop filter. Fabricated on a 0.18-m CMOS process, the modulator achieves a peak SNDR of 74 dB in a 25 kHz bandwidth, and occupies an area of 0.6 mm 2 ; the modulator core consumes 300 W. Index Terms-Body-input circuit, continuous-time delta-sigma modulator, return-to-zero signaling, ultra-low-voltage circuit.
A 3.3V Single-Poly CMOS Audio ADC Delta-Sigma Modulator with 98dB Peak SINAD
2000
This paper presents a second-order 16 modulator for audio-band analog-to-digital conversion implemented in a 3.3-V, 0.5-µm, single-poly CMOS process using metal-metal capacitors that achieves 98-dB peak signal-to-noise-and-distortion ratio and 105-dB peak spurious-free dynamic range. The design uses a low-complexity, first-order mismatch-shaping 33-level digital-to-analog converter and a 33-level flash analog-to-digital converter with digital common-mode rejection and dynamic element matching of comparator offsets. These signal-processing innovations, combined with established circuit techniques, enable state-of-the-art performance in CMOS technology optimized for digital circuits.
This paper presents a design of a switched-capacitor discrete time 1st order Delta-Sigma modulator used for a resolution of 8 bits Sigma-Delta analog to digital converter. For lower power consumption, the use of operational transconductance amplifier is necessary in order to provide wide output voltage swing and moderate DC gain. Simulation results showed that with 0.35um CMOS technology, 80 KHz signal bandwidth and oversampling rate of 64, the modulator achieved 49.25 dB Signal to Noise Ratio (SNR) and the power consumption was 5.5 mW under ±1.5V supply voltage .
This paper presents a design of a switched-capacitor discrete time 1st order Delta-Sigma modulator used for a resolution of 8 bits Sigma-Delta analog to digital converter. For lower power consumption, the use of operational transconductance amplifier is necessary in order to provide wide output voltage swing and moderate DC gain. Simulation results showed that with 0.35um CMOS technology, 80 KHz signal bandwidth and oversampling rate of 64, the modulator achieved 49.25 dB Signal to Noise Ratio (SNR) and the power consumption was 5.5 mW under ±1.5V supply voltage .
International Journal of Research in Engineering and Technology, 2013
This paper presents a design of a switched-capacitor discrete time 1st order Delta-Sigma modulator used for a resolution of 8 bits Sigma-Delta analog to digital converter. For lower power consumption, the use of operational transconductance amplifier is necessary in order to provide wide output voltage swing and moderate DC gain. Simulation results showed that with 0.35um CMOS technology, 80 KHz signal bandwidth and oversampling rate of 64, the modulator achieved 49.25 dB Signal to Noise Ratio (SNR) and the power consumption was 5.5 mW under ±1.5V supply voltage .
A 900 mV 40 μW switched opamp ΔΣ modulator with 77 dB dynamic range
1998
Portable electronic systems require low-voltage low-power building blocks. An important building block is an A/D converter. /spl Delta//spl Sigma/ ADCs provide an efficient way of trading off speed for resolution. The switched op amp (SO) technique allows design of switched-capacitor (SC) circuits at very low supply voltage without the use of multithreshold technologies or voltage multipliers to drive the switches. The basic idea of it is to leave out the switches connected to the output of the amplifier in a SC integrator, because those are the ones that fail to conduct when the supply voltage is low. Switches can only be connected to well-chosen reference voltages. In this implementation the differential modified SO integrator cell is used, so the reference voltages are V/sub SS/ and V/sub DD/. This allows maximum overdrive of V/sub DD/-V/sub SS/ for the switches.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017
A 4-bit, third-order, continuous-time modulator is presented for use in wireless communications systems. Based on small-signal noise models, analyses for reducing noise in the feedback digital-to-analog converter (DAC) are presented in detail. This enables easy performance/area optimization for the DAC unit elements and the RC noise filter in the DAC bias circuits. To obtain high linearity while simplifying the DAC design, circuit-and layout-level design techniques for minimizing switching time mismatches among and inside the DAC unit elements are presented. As a result, glitch-induced harmonic distortion is greatly reduced, requiring only a simple dataweighted averaging for the multibit DAC. In combination with multipath multistage op amps used to implement active-RC integrators, the presented techniques make it feasible to design a high-performance modulator with low power and small area, which is desired in many wireless communications systems. The experimental prototype, implemented in a 28-nm CMOS technology, achieves a 72.6-dB dynamic range, a 70.7-dB peak SNR, and a 70.1-dB peak signal-to-noise plus distortion ratio for a signal bandwidth of 20 MHz. The total power consumption is 6 mW from a 1-and 1.4-V supply, of which analog and digital circuits dissipate 4.5 and 1.5 mW, respectively. The total active area is 0.058 mm 2 .