A New Redundant Binary Booth Encoding for Fast Bit Multiplier Design (original) (raw)

High-speed Multiplier Design Using Multi-Operand Multipliers

2012

Multipliers are used in most arithmetic computing systems such as 3D graphics, signal processing, and etc. It is inherently a slow operation as a large number of partial products are added to produce the result. There has been much work done on designing multipliers [1]-[6]. In first stage, Multiplication is implemented by accumulation of partial products, each of which is conceptually produced via multiplying the whole multi-digit multiplicand by a weighted digit of multiplier. To compute partial products, most of the approaches employ the Modified Booth Encoding (MBE) approach [3]-[5], [7], for the first step because of its ability to cut the number of partial products rows in half. In next step the partial products are reduced to a row of sums and a row of caries which is called reduction stage.

A Simple High-Speed Multiplier Design

IEEE Transactions on Computers, 2000

The performance of multiplication is crucial for multimedia applications such as 3D graphics and signal processing systems, which depend on the execution of large numbers of multiplications. Previously reported algorithms mainly focused on rapidly reducing the partial products rows down to final sums and carries used for the final accumulation. These techniques mostly rely on circuit optimization and minimization of the critical paths. In this paper, an algorithm to achieve fast multiplication in two's complement representation is presented. Rather than focusing on reducing the partial products rows down to final sums and carries, our approach strives to generate fewer partial products rows. In turn, this influences the speed of the multiplication, even before applying partial products reduction techniques. Fewer partial products rows are produced, thereby lowering the overall operation time. In addition to the speed improvement, our algorithm results in a true diamond-shape for the partial product tree, which is more efficient in terms of implementation. The synthesis results of our multiplication algorithm using the Artisan TSMC 0:13um 1.2-Volt standard-cell library show 13 percent improvement in speed and 14 percent improvement in power savings for 8-bit  8-bit multiplications (10 percent and 3 percent, respectively, for 16-bit  16-bit multiplications) when compared to conventional multiplication algorithms.

Design and Development of 8-Bits Fast Multiplier for Low Power Applications

International Journal of Engineering and Technology, 2012

High speed multiplication has always been a fundamental requirement of high performance processors and systems. With MOS scaling and technological advances there is a need for design and development of high speed data path operators such as adders and multipliers to perform signal processing operations at very high speed supporting higher data rates. In DSP applications, multiplication is one of the most utilized arithmetic operations as part of filters, convolves and transforms processors. Improving multipliers design directly benefits the high performance embedded processors used in consumer and industrial electronic products. Hence there is a need for design and development of high-speed architectures for N-bit multipliers supporting high speed and power. Here we review the architecture reported in the literature for multipliers and critical issues degrading the speed and power of these multiplier. Based on this review suitable modifications are suggested in the design for high speed and low power multipliers.

Review on Performance and Hardware Complexity of Multipliers

Multiplier is a key component which is majorly used in Digital electronics and Digital Signal Processing.Multiplier is a component or electronic circuit which gives product of two binary numbers. Multiplier with high speed, low power consumption and less size is preferred in the Digital Electronic field. That's why Multipliers with low power consumption and low hardware complexity got huge demand and it is always challenging to create a multiplier with these specifications. There are different Multipliers but most popular among them are Wallace Multiplier,Braun Multiplier and Dadda Multiplier.These Multipliers are differed according to their respective algorithms.Here we majorly discussed about 90 nm technology. In this paper, we discuss and review on low power multipliers with it's hardware and performance with comparisons.

An Efficient 16-Bit Multiplier based on Booth Algorithm

International Journal of Advancements in Research & Technology, Volume 1, Issue 6, November-2012 ISSN 2278-7763, 2012

Multipliers are key components of many high performance systems such as microprocessors, digital signal processors, etc. Optimizing the speed and area of the multiplier is major design issue which is usually conflicting constraint so that improving speed results mostly in bigger areas. A VHDL designed architecture based on booth multiplication algorithm is proposed which not only optimize speed but also efficient on energy use.

Design of Efficient and Fast Multiplier Using MB Recoding Techniques

International Journal of Emerging Research in Management &Technology , 2015

In Digital Signal processing applications, fast processing of a huge quantity of data in Digital form. Presently, multiplier plays a major role in Digital Signal Processors. Using three different schemes in Fused Add-Multiply (FAM) design for the reduction in terms of power and delay. Multiplier results of 7 bit and 11 bit (odd) for both signed and unsigned numbers to be produced using efficient modified booth recoding (EMBR) techniques in three different schemes of FAM design.

Design of 16-bit Multiplier Using Efficient Recoding Techniques

International Journal of Hybrid Information Technology, 2015

Multiplier is the major component for processing of large amount of data in DSP applications. Using different recoding schemes in Fused Add-Multiply (FAM) design for the reduction of power and look up tables. The performance of 16-bit signed and unsigned multipliers were designed and obtained results are tabulated using Efficient Modified Booth Recoding (EMBR) techniques, which can be used for low power applications.

Design and Comparison of High Speed Radix-8 and Radix-16 Booth's Multipliers

Multiplier is one of the hardware block which generally occupies a significant chip area and is required to be minimized which will be fruitful to number of applications in which multiplier blocks constitute an important unit such as digital signal processing (DSP) systems or computational techniques. Battery operated systems require low power devices to be implemented which can be minimized if the hardware required for the device is reduced logically. This paper focuses the DSP applications in which multiplier is significantly used and proposes a technique that helps in reducing the hardware as well as delay leading to the rise in performance of the system thus helping in increasing the operation frequency by a significant value. A 16-bit multiplier has been designed using a radix-8 and radix-16 Booth's multiplication that reduces number of partial products.

Design and Implementation of Efficient Multiplier Architectures

The main purpose of the project is to improve the speed of the digital circuits like multiplier since adder and multiplier are one of the key hardware components in high performance systems such as microprocessors, digital signal processors and FIR filters etc. Hence we always try for efficient multiplier architecture to increase the efficiency and performance of a system. The efficiency of the multiplier can be improved by applying Vedic sutras. This 'Vedic Mathematics' is the name given to the ancient system of mathematics or, to be precise, a unique mathematical problem can done with the help of arithmetic, algebra, geometry or trigonometry can be solved. Multiplication plays an important role in the processors. It is one of the basic arithmetic operations and it requires more hardware resources and processing time than the other arithmetic operations. Vedic mathematic is the ancient Indian system of mathematic. It has a unique technique of calculations based on 16 Sutras. The multiplication sutra between these 16 sutras is the UrdhvaTiryakbhyam sutra which means vertical and crosswise. In this project high speed, low power 2x2 and 4x4 multipliers are designed and corresponding layout is generated using Microwind Version 3.1.