A New Redundant Binary Booth Encoding for Fast Bit Multiplier Design (original) (raw)

The paper presents a novel approach to Booth encoding for redundant binary (RB) arithmetic aimed at enhancing the performance of digital multipliers. It addresses the challenges of generating hard multiples and the complexities involved in converting normal binary (NB) to RB representations in multiplier designs. The proposed RB Booth encoding technique polarizes adjacent encoded digits to directly produce RB partial products, mitigating the need for hard multiples and correction vectors, ultimately yielding a 14% increase in speed and a 17% reduction in energy-delay product compared to existing algorithms across various word lengths.