GeSn p-FinFETs with Sub-10 nm Fin Width Realized on a 200 mm GeSnOI Substrate: Lowest SS of 63 mV/decade, Highest Gm,int of 900 µS/µm, and High-Field µeff of 275 cm2/V•s (original) (raw)

2018 IEEE Symposium on VLSI Technology, 2018

Abstract

We report the first GeSn p-FinFETs with sub-10 nm fin width (W<inf>Fin</inf>) enabled by the formation of the first 200 mm GeSn-on-insulator (GeSnOI) substrate and a self-limiting digital etch for accurate control of the fin dimension, achieving a fin with a top width of 5 nm. Owing to the excellent gate control using extremely scaled GeSn fin and the good GeSn fin quality maintained using a device fabrication process with low thermal budget, an SS of 63 mV/decade was achieved at channel length (L<inf>CH</inf>) of 50 nm, which is a record low for Ge-based p-FETs. Furthermore, record high G<inf>m,int</inf> of 900 μS/µm (V<inf>DS</inf> of -0.5 V) and G<inf>m,int</inf>/S<inf>sat</inf> of 10.5 for GeSn p-FETs were achieved. A high high-field hole mobility µ<inf>eff</inf> of 275 cm²/V•s (at inversion carrier density N<inf>inv</inf> of 8×10¹² cm<...

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