Techniques for formal verification of digital systems: a system approach (original) (raw)

A New High Level Model Based on Integer Equations to Check CTL Properties in VHDL Environment

This paper describes the use of integer equations for high level modeling of digital circuits for rule-based formal verification at this level. BDD operations are not applicable to a large datapath because of large CPU time and memory usage. In our method, a behavioral state machine is represented by a list of integer equations, and RT level properties are directly applied to this representation. Furthermore, this method is applied to circuits without having to separate their data and control sections. For this implementation, we use a canonical form of integer equations, which simplifies equations instead of solving them. This paper compares our results with those of the VIS verification tool that is a BDD based program.

Application of Model Checking to the Verification of Digital Systems

2009

The article presented here deals with the verification of a digital design using temporal logic and model checking. Temporal logic has been used as a specification language to catch the behaviour of the system design and model checking has been chosen as a verification method to evaluate the design accuracy. As a digital system to be modelled and verified we have chosen the sequence detector; the detected string is 010. To compare the way how to establish temporal model and its properties and to see better coincidences and differences in describing their behaviour we made up the model of the sequence detector in two variants: without and with overlapping. We took, as finite state machine (FSM), the both automata, the Moore as well as the Mealy, each considered without and with overlapping. After the temporal properties of the four drawn models had been defined we wrote respective programs corresponding to each of models, in SMV language, to pass them as input files into the SMV mode...

Formal specification in VHDL for hardware verification

In this paper, we enrich VHDL with new specification constructs intended for hardware verification. Using our extensions, total correctness properties may now be stated whereas only partial correctness can be expressed using the standard VHDL assert statement. All relevant properties can now be specified in such a way that the designer does not need to use formalisms like temporal logics. As the specifications are independent from a certain formalism, there is no restriction to a certain hardware verification approach.

FSM modeling of synchronous VHDL design for symbolic model checking

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198), 1999

In this paper, we defined a new FSM model that based on the synchronous behavior and symbolic representation technique. The algorithm to elaborate the model from the VHDL description of synchronous circuits is presented. By eliminating the unnesessary transition function, our model has much less states than Deharbe's mixed model[1]. The exprimental results demonstrate the model and modeling method can make symbolic model checking more practical.

Specification of control flow properties for verification of synthesized VHDL designs

Lecture Notes in Computer Science, 1996

Behavioral specifications in VHDL contain multiple communicating processes. Register level designs synthesized from these specifications contain a data path represented as a netlist and a controller consisting of multiple communicating synchronous finite state machines. These finite state machines together implement the control flow specified in and implied by the behavioral specification in VHDL. This paper describes a systematic approach to identifying the control flow properties critical to the proper functioning of designs synthesized from VHDL. These properties are then formulated as specifications in Computational Tree Logic (CTL) while presenting a controller model for high-level synthesis. These specifications form a necessary set that must be satisfied by any correct synthesized design. A high-level synthesis system, as a byproduct of creating RTL designs, can automatically generate these CTL specifications.

An efficient algorithm for real-time symbolic model checking

Proceedings ED&TC European Design and Test Conference, 1996

The verification of real-time properties requires model checking techniques for quantitative temporal structures and real-time temporal logics. However, up to now, most of those problems were solved by a translation into a standard CTL model checking problem with unit-delay structures. Although usual CTL model checkers like SMV can be used then, the translation leads to large structures and CTL formulas, such that the verification requires large computation times and only small circuits can be verified. In this paper a new model checking algorithm for quantitative temporal structures and quantitative temporal logic is presented, which avoids these drawbacks. Motivated by lowlevel circuit verification, the implemented prover can be used for verifying general real-time systems. Although it has been proved that the complexity of the new algorithm is identical to the corresponding CTL model checking problem, the application of the new algorithms leads to significant better runtimes and larger verifiable structures. The paper presents the underlying algorithms, the complexity proof, implementational issues and concludes with experimental results, demonstrating the advantages of our approach.

A model checking framework for hierarchical systems

2011 26th IEEE/ACM International Conference on Automated Software Engineering (ASE 2011), 2011

BDD-based symbolic model checking is capable of verifying systems with a large number of states. In this work, we report an extensible framework to facilitate symbolic encoding and checking of hierarchical systems. Firstly, a novel library of symbolic encoding functions for compositional operators (e.g., parallel composition, sequential composition, choice operator, etc.) are developed so that users can apply symbolic model checking techniques to hierarchical systems with little knowledge of symbolic encoding techniques (like BDD or CUDD). Secondly, as the library is language-independent, we build an extensible framework with various symbolic model checking algorithms so that the library can be easily applied to encode and verify different modeling languages. Lastly, the applicability and scalability of our framework are demonstrated by applying the framework in the development of symbolic model checkers for three modeling languages as well as a comparison with the NuSMV model checker.

Formal verification of VHDL using VHDL-like ACL2 models

Electronic Chips & Systems Design Languages, 2001

When a design reaches the register transfer level, essential architectural decisions have been taken; their validation required extensive simulation of the abstract behavioral specifications. The recognized need for formal verification cannot be met by current automatic equivalence and model checking tools, which mainly apply to logic synthesis inputs and outputs, or require manual abstraction. We propose to introduce mechanically supported formal reasoning in the design flow, by producing a model of VHDL behavioral specifications in the logic of the ACL2 theorem prover. Written in Lisp, this model is executable as well as subject to symbolic manipulations. We define the semantics of VHDL data types and behavioral-style statements in the logic. We use macros to generate names, function definitions and theorems automatically, by instantiation of model skeletons, while retaining an algorithmic syntactic flavor. This feature is particularly useful to translate VHDL statements into resembling ACL2 macros, so that the logic formalization remains readable.