A High Density and Low Power Cache Based on Novel SRAM Cell (original) (raw)
Related papers
2013
Abstract—This paper presents a novel CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20 % smaller than a conventional six-transistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform from another side of cell, and swing voltage reduced on word-lines thus dynamic power during read/write operation reduced. The fabrication process is fully compatible with high-performance CMOS logic technologies, because there is no need to integrate a poly-Si resistor or a TFT load. HSPICE simulation in standard 0.25µm CMOS technology confirms all results obtained from this paper. Keywords—Positive feedback, leakage current, read operation, write operation, dynamic energy consumption. I.
A Novel Four-Transistor SRAM Cell with Low Dynamic Power Consumption
This paper presents a novel CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20% smaller than a conventional six-transistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform from another side of cell, and swing voltage reduced on word-lines thus dynamic power during read/write operation reduced. The fabrication process is fully compatible with high-performance CMOS logic technologies, because there is no need to integrate a poly-Si resistor or a TFT load. HSPICE simulation in standard 0.25µm CMOS technology confirms all results obtained from this paper.
Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoC
2010
This paper addresses a novel five-transistor (5T) CMOS SRAM design with high performance and reliability in 65nm CMOS, and illustrates how it reduces the dynamic power consumption in comparison with the conventional and low-power 6T SRAM counterparts. This design can be used as cache memory in processors and lowpower portable devices. The proposed SRAM cell features ~13% area reduction compared to a conventional 6T cell, and features a unique bit-line and negative supply voltage biasing methodology and ground control architecture to enhance performance, and suppress standby leakage power.
High Read Stability and Low Leakage Cache Memory Cell
2007 IEEE International Symposium on Circuits and Systems, 2007
Data in conventional six transistor (6T) static random access memory (SRAM) cells are vulnerable to noise due to the direct access to the data storage nodes through the bit lines during a read operation. A new nine transistor (9T) SRAM cell is proposed in this paper for simultaneously enhancing read stability and reducing leakage power consumption. The proposed 9T SRAM cell isolates the data from the bit lines during a read operation. The read static-noise-margin (SNM) of the proposed circuit is enhanced by 2× as compared to a standard 6T SRAM cell in a 65 nm CMOS technology. Furthermore, leakage power consumption of the new 9T SRAM cell is reduced by 22.9% as compared to the 6T SRAM cell. The read stability enhancement and leakage power reduction provided by the new circuit technique are also verified under process parameter variations.
Performance and Power Solutions for Caches Using 8T SRAM Cells
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture Workshops, 2012
Voltage scaling can reduce power dissipation significantly. SRAM cells (which are traditionally implemented using six-transistor cells) can limit voltage scaling due to stability concerns. Eight-transistor (8T) cells were proposed to enhance cell stability under voltage scaling. 8T cells, however, suffer from costly write operations caused by the column selection issue. Previous work has proposed Read-Modify-Write (RMW) to address this issue at the expense of an increase in cache access frequency. In this work, we introduce two microarchitectural solutions to address this inefficiency. Our solutions rely on grouping write accesses and bypassing read accesses made to the same cache set. We reduce cache access frequency up to 55%.
A Novel Low Power Design of SRAM cell and its Performance Analysis
2011
SRAM is a type of semiconductor memory which does not need to be periodically refreshed. With scaling down of the technology, the feature sizes have shrink more and more and miniaturization at chip level has occurred. But as a trade off, the demand for power has also increased. SRAM continues to be a critical component across a gamut of microelectronics applications. Leakage is a serious problem particularly for SRAM. To address sub threshold leakage issue sleepy stack approach is used .The sleepy stack SRAM cell design, is a new technique which involves changing the circuit structure as well as using high-V th. The sleepy stack technique achieves greatly reduced leakage power while maintaining precise logic state in sleep mode. This paper compares performance of SRAM using sleepy stack approach with that of conventional design. The impact of temperature and voltage on the performance of sleepy stack design is also analyzed. Berkeley Predictive Technology Model (BPTM), level 49 targeting 0.18μm technology is used. The design is successfully simulated and analyzed using HSPICE tools.
Low Power High Performance (LPHP) SRAM Cell for Write Operation
Background: Presently, living in a predominantly electronics world, the current technology requires lower system power consumption for many applications, due to dramatic growth in applications that consume less power and high performance. Power consumption plays vital role in mobile devices and battery powered portable electronic system. The conventional 6T SRAM cell is susceptible in power consumption. Objective: To propose new Low power High Performance SRAM architecture to reduce the power consumption during write 0 and write 1 operation because the cache write consumes considerable large power due to full voltage swing on the bit-line. Results: The simulated results shows the write power consumption reduced approximately 77.4% and faster response compared to the Conventional 6T SRAM cell due to single Bit Line (BL) technique during write operation. Both read delay and static noise margin are maintained same as the 6T cell after carefully sizing of all the transistors. Conclusion: In the proposed cell, the two extra transistors to connect or disconnect the feedback connection between the two back to back inverters during write operation and hence the write activity factor is reduced which makes the proposed cell consumes less power during write operations compared with the conventional cell.
Design and Analysis of 6 T SRAM Cell with low Power Dissipation
2012
In the current technology demand for SRAM is increasing drastically due to its usage in almost all embedded systems, forms a integral part of computer, System On Chip and high performance processors and VLSI circuits etc. The Power Consumption has become a major concern in Very Large Scale Integration circuit designs and reducing the power dissipation has become challenge to the Low power VLSI designers. As power dissipation increases with the scaling of the technologies. As the feature size shrinks ,static power has become a great challenge for current and future technologies. In this research work, we design 6T SRAM and some of the techniques to reduce the leakage power using like sleep approach, stack approach techniques which reduces the leakage power without changing the exact operation of SRAM. The proposed circuits were designed in 0.18um CMOS VLSI technology with a Microwind tool, and measure the power dissipation for the different design approach in Advanced BSIM4 level. Po...
Design of low-leakage and high writable proposed SRAM cell structure
2014 International Conference on Electronics and Communication Systems (ICECS), 2014
The high demand of embedding more and more functionality in a single chip has enforced the use of scaling. As scaling drastically reduce the channel length the leakage current also increases significantly which increases the static power dissipation. A novel 8T-SRAM cell (Leakage Current Reduced SRAM cell) is proposed which reduces the leakage power dissipation significantly in comparison to the conventional 6T-SRAM cell. The cell is designed using GPDK-90 nm technology library and simulated under Cadence Virtuoso design environment. The proposed cell uses a lower voltage than Vdd during standby mode which leads to a reduction of leakage current and hence the static power consumption. The lower voltage is generated using an NMOS which creates a threshold voltage drop when transfer a high logic. The power consumption is found to be 25.02 % lesser than that of conventional six transistors SRAM cell .The stability and the write ability are measured using the N-Curve technique.