Verifying Sequential Consistency on Shared-Memory Multiprocessors by Model Checking (original) (raw)

Verifying sequentially consistent memory

Distributed Computing, 1994

In distributed shared memory architectures, memory usually obeys weaker constraints than that of ordinary memory in (cache-less) single processor systems. One popular weakening is that of sequential cOl1Jisfency. Proving that a memory is sequentialy consistent does not easily fit the standard refinemcnt and vcrification strategies. This paper takes a sequential consistent memory-the lazy caching protocol-and verifies it using a number of verification approaches. In almost all cases, existing approaches have to be generalized first.

Gradual Consistency Checking

Computer Aided Verification

We address the problem of checking that computations of a shared memory implementation (with write and read operations) adheres to some given consistency model. It is known that checking conformance to Sequential Consistency (SC) for a given computation is NP-hard, and the same holds for checking Total Store Order (TSO) conformance. This poses a serious issue for the design of scalable verification or testing techniques for these important memory models. In this paper, we tackle this issue by providing an approach that avoids hitting systematically the worst-case complexity. The idea is to consider, as an intermediary step, the problem of checking weaker criteria that are as strong as possible while they are still checkable in polynomial time (in the size of the computation). The criteria we consider are new variations of causal consistency suitably defined for our purpose. The advantage of our approach is that in many cases (1) it can catch violations of SC/TSO early using these weaker criteria that are efficiently checkable, and (2) when a computation is causally consistent (according to our newly defined criteria), the work done for establishing this fact simplifies significantly the work required for checking SC/TSO conformance. We have implemented our algorithms and carried out several experiments on realistic cache-coherence protocols showing the efficiency of our approach.

Formally Verifying the Distributed Shared Memory Weak Consistency Models

2006 International Conference on Advanced Computing and Communications, 2006

A specifi cation and verifi cation methodology for Distributed Shared Memory (DSM) consistency models specifi cally weak consistency model is proposed. For this, we designed and implemented abstract DSM System. In DSM system, sequential consistency unnecessarily reduces the performance of the system because it does not allow to reorder or pipeline the memory operations. Relaxed memory consistency allows reordering of memory events and buffering or pipelining of memory accesses. So that relaxed consistency improves the performance of the DSM system. For any critical system, it is very important to develop methods that increase our confi dence in the correctness of such systems. One of such methods for checking the correctness of critical system is formal verifi cation. For verifi cation of weak consistency models we specify the weak consistency properties and are verifi ed on Abstract DSM System using CADP Tool box.

On Composition and Implementation of Sequential Consistency (Extended Version)

ArXiv, 2016

It has been proved that to implement a linearizable shared memory in synchronous message-passing systems it is necessary to wait for a time proportional to the uncertainty in the latency of the network for both read and write operations, while waiting during read or during write operations is sufficient for sequential consistency. This paper extends this result to crash-prone asynchronous systems. We propose a distributed algorithm that builds a sequentially consistent shared memory abstraction with snapshot on top of an asynchronous message-passing system where less than half of the processes may crash. We prove that it is only necessary to wait when a read/snapshot is immediately preceded by a write on the same process. We also show that sequential consistency is composable in some cases commonly encountered: 1) objects that would be linearizable if they were implemented on top of a linearizable memory become sequentially consistent when implemented on top of a sequential memory w...

Fast complete memory consistency verification

2009

The verification of an execution against memory consistency is known to be NP-hard. This paper proposes a novel fast memory consistency verification method by identifying a new natural partial order: time order. In multiprocessor systems with store atomicity, a time order restriction exists between two operations whose pending periods are disjoint: the former operation in time order must be observed by the latter operation. Based on the time order restriction, memory consistency verification is localized: for any operation, both inferring related orders and checking related cycles need to take into account only a bounded number of operations.

Toward transparent selective sequential consistency in distributed shared memory systems

Proceedings. 18th International Conference on Distributed Computing Systems (Cat. No.98CB36183), 1998

This paper proposes a transparent selective sequential consistency approach to Distributed Shared Memory (DSM) systems. First, three basic techniques | time selection, processor selection, and data selection { are analyzed for improving the performance of strictly sequential consistency DSM systems, and a transparent approach to achieving these selections is proposed. Then, this paper focuses on the protocols and techniques devised to achieve transparent data selection, including a novel Selective Lazy/Eager Updates Propagation protocol for propagating updates on shared data objects, and the Critical Region Updated Pages Set scheme to automatically detect the associations between shared data objects and synchronization objects. The proposed approach is able to o er the same potential performance advantages as the Entry Consistency model or the Scope Consistency model, but it imposes no extra burden to programmers and never fails to execute programs correctly. The devised protocols and techniques have been implemented and experimented with in the context of the TreadMarks DSM system. Performance results have shown that for many applications, our transparent data selection approach outperforms the Lazy Release Consistency model using a lazy or eager updates propagation protocol.

Implementing sequential consistency in cache-based systems

1990

A model for shared-memory systems commonly (and often implicitly) assumed by programmers is that of sequential consistency. For implementing sequential consistency in a cache-based system, it is widely believed that (1) implementing strong ordering is sufficient and restricting a processor to one sharedmemory reference at a time is practically necessary.

A View-based Consistency Model based on Transparent Data Selection in Distributed Shared Memory

2001

This paper proposes a novel View-based Consistency model for Distributed Shared Memory, in which a new concept, view, is coined. A view is a set of data objects that a pro- cessor has the right to access in the shared memory. The View-based Consistency model only requires that the data objects of a processor's view are updated before a processor accesses them. In this way, it can achieve the maximum relaxation of constraints on mod- ification propagation and execution in data-race-free programs. This paper first briefly reviews a number of related consistency models in terms of their use of three techniques - time, processor and data selection - which each eliminate some unnecessary propaga- tion of memory modifications while guaranteeing sequential consistency for data-race-free programs. Then, we present the View-based Consistency model and its implementation. In contrast with other models, the View-based Consistency model can achieve transparent data selection without progra...

Formal verification of coherence for a shared memory multiprocessor model

Parallel Computing Technologies, 2001

The specification and verification of shared-memory multiprocessor cache coherence protocols is a paradigmatic example of parallel technologies where formal methods can be applied. In this paper we present the specification and verification of a cache protocol and a set of formalisms which are based on 'process theory'. System correctness is not established by simple techniques such as testing and simulation, but 'ensured'in terms of the underlying formalism. In order to manipulate the specification and verify the properties we have used ...