A 2-5.5 GHz Beamsteering Receiver IC With 4-Element Vivaldi Antenna Array (original) (raw)
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IEEE Journal of Solid-State Circuits
This paper presents a 28-GHz CMOS four-element phased-array transceiver chip for the fifth-generation mobile network (5G) new radio (NR). The proposed transceiver is based on the local-oscillator (LO) phase-shifting architecture, and it achieves quasi-continuous phase tuning with less than 0.2-dB radio frequency (RF) gain variation and 0.3 • phase error. Accurate beam control with suppressed sidelobe level during beam steering could be supported by this work. At 28 GHz, a single-element transmitter-mode output P 1 dB of 15.7 dBm and a receiver-mode noise figure (NF) of 4.1 dB are achieved. The eight-element transceiver modules developed in this work are capable of scanning the beam from −50 • to +50 • with less than −9-dB sidelobe level. A saturated equivalent isotropic radiated power (EIRP) of 39.8 dBm is achieved at 0 • scan. In a 5-m overthe-air measurement, the proposed module demonstrates the first 512 quadrature amplitude modulation (QAM) constellation in the 28-GHz band. A data stream of 6.4 Gb/s in 256-QAM could be supported within a beam angle of ±50 • . The achieved maximum data rate is 15 Gb/s in 64-QAM. The proposed transceiver chip consumes 1.2 W/chip in transmitter mode and 0.59 W/chip in receiver mode. Index Terms-28 GHz, 256 quadrature amplitude modulation (QAM), 512-QAM, beamforming, CMOS, error vector magnitude (EVM), fifth-generation mobile network (5G) new radio (NR), local-oscillator (LO) phase shifter, phased array, transceiver.
A 3-43ps time-delay cell for LO phase-shifting in 1.5-6.5GHz beamsteering receiver
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS), 2018
This paper describes a digital-friendly passives-less time delay cell that generates programmable phase-shifts for downconverting front-end in LO-based beamsteering receiver. Cell design supports 1.5-6.5GHz broadband receiver operation and cell layout occupies an area of only 15x16.5µm 2 including power supply rails and control logic. Simulated in 28nm CMOS technology, delay cell exhibits 6 distinct delay values {3, 3.5, 17, 19, 24, 43}ps consuming at most 220µW@1V.
A Delay-Based LO Phase-Shifting Generator for a 2-5GHz Beamsteering Receiver in 28nm CMOS
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)
This paper proposes a wideband 2-5GHz LO phaseshifting generator based on two digitally controlled delay lines. The concept is verified on a two-channel beamsteering directconversion receiver prototype implemented in 28nm CMOS. The novel generator provides both tunable phase-shifting and generation of I/Q components, achieving picosecond time resolution. The generator consumes 4.5-11.2mW and occupies 0.021mm 2 .
A fully integrated 4 × 2 element CMOS RF phased array receiver for 5G
Analog Integrated Circuits and Signal Processing
This paper presents a fully integrated phased array receiver containing two four element Radio Frequency (RF) Beamforming (BF) receivers supporting two Multiple-Input Multiple-Output (MIMO) channels. The receivers are designed and fabricated using 45nm CMOS SOI technology. A 10 bit IQ vector modulator phase shifter (IQVM) is implemented in RF signal paths to control the phase and amplitude of the received signal before combining. Each IQVM provides 360 degree phase shift control and 17 dB gain variation. An off-chip, simultaneous high-Q impedance matching and bandpass filtering technique for each low-noise amplifiers (LNA) is presented using non-uniform transmission line (NUTL) segments. Measured downconversion gain at 100 MHz Intermediate Frequency (IF) and noise figure (NF) of a single path are 23 dB and 5.4dB, respectively, giving estimated 3.4 dB NF for a single element when simulated PCB and matching losses are taken into account. 1 dB compression and Input third-order intercept point (IIP3) are-37 dBm and-28 dBm, respectively. Each four-element receiver consumes 486 mW DC power from 1.2V power supply. Total area of two receivers is 5.69 mm2.
A four channel phased array transmitter using an active RF phase shifter for 5G wireless systems
Analog Integrated Circuits and Signal Processing
This paper presents a four channel phased array transmitter at 15 GHz aimed for the upcoming 5G wireless systems. The circuit is designed and fabricated using 45 nm CMOS silicon on insulator (SOI) technology. The design is programmable with exhaustive digital controls available for parameters such as bias voltage, resonance frequency, and gain. The phase shift required for the phased array is provided at RF using an IQ vector modulator (IQVM) topology, which provides both amplitude and phase control. Based on the measurement results, the IQVM provides 360 degree of phase shift and 15 dB of gain variation. Both phase and amplitude information are encoded in a 10 bit control word. The mean angular separation provided by the IQVM is 3 degree at optimum amplitude levels. Active area occupied is 2.88 square millimeter. Total DC power consumed by one transmit channel from 1 V and 2.6 V supply is 268 mW. The maximum RF output power from one transmit channel is 1 dBm. Measured EVM for a 256 QAM modulated signal is as low as 2.0%. All results include the impact of printed circuit board (PCB) traces and pad parasitics. Based on the achieved results, the proposed architecture is well suited for the next generation of the wireless systems.
A 45nm CMOS SOI, four element phased array receiver supporting two MIMO channels for 5G
2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2017
A four element, two channel Multiple-Input Multiple-Output (MIMO) phased array receiver at 15 GHz is designed and fabricated in 45nm CMOS SOI process. The receiver consists of two independent four-antenna phasedarrays for hybrid beamforming and MIMO processing in digital domain. Phase and amplitude control is based on RF IQ vector modulator (VM) at carrier frequency. Measured downconversion gain and noise figure (NF) of one path are 23 dB and 5.4dB, respectively, giving estimated 3.4 dB NF for the IC when simulated PCB and matching losses are taken into account. 1 dB compression and IIP3 points are −37 dBm and −28 dBm, respectively. One phased array consumes 486 mW DC power from 1.2V power supply. Total chip area is 5.69 mm2.
A 28 GHz four-channel phased-array transceiver in 65-nm CMOS technology for 5G applications
AEU - International Journal of Electronics and Communications, 2019
A 28GHz fully integrated 4-channel TX/RX 5G beam-forming transceiver is implemented in 65-nm CMOS technology. Each TX/RX channel can be digitally controlled with 5.625 • phase step and 2 dB gain step. The transceiver employs a heterodyne architecture with 6 GHz intermediate frequency (IF). The transciever works in a band of frequencies between 26GHz and 30GHz. The up/down-conversion mixers are integrated on the same chip with a shared LO chain. The phased-array power combining/splitting is done using a Wilkinson power combiner/divider. Each channel features 3.4 to 3.9 dB NF and-5 to-3.5 dBm IIP3 in RX mode, high OP1dB of 14.7 dBm and 18 dB gain in TX mode. The maximum rms amplitude and phase error for each channel is 0.25 dB and 1.5 • across gain and phase states, respectively. The RFIC area is 5.29x3.4 mm 2 including pads and it consumes 240 mW per channel in TX mode, 120 mW per channel in RX mode and 174 mW for the LO chain with a total power of 1.58 W from a 1.2 V supply.
2016
Next-generation mobile technology (5G) aims to provide an improved experience through higher data-rates, lower latency, and improved link robustness. Millimeter-wave phased arrays offer a path to support multiple users at high datarates using high-bandwidth directional links between the base station and mobile devices. To realize this vision, a phased-array-based pico-cell must support a large number of precisely controlled beams, yet be compact and power efficient. These system goals have significant mm-wave radio interface implications, including scalability of the RFIC+antenna-array solution, increase in the number of concurrent beams by supporting dual polarization, precise beam steering, and high output power without sacrificing TX power efficiency. Packaged Si-based phased arrays [1-3] with nonconcurrent dual-polarized TX and RX operation [2,3], concurrent dual-polarized RX operation [3] and multi-IC scaling [3,4] have been demonstrated. However, support for concurrent dual-po...
Advanced Phased Array Transceivers for Enabling Next-Generation 5G Communication Networks
Journal of Electronics and Electrical Engineering, 2023
This article presents advancements and key considerations in the design implementation of phased array transceivers for the fifth-generation (5G) communication networks. It emphasizes the significance of careful consideration and system-level optimization to realize the full potential of phased array transceivers. The focus is on antenna elements and beamforming techniques with a detailed discussion on different types of beamforming techniques used in wireless communication systems. These include analog, digital, and hybrid beamforming. The article starts by introducing the concept of a phase shifter, which is a crucial component in controlling the phase of the transmitted signal. It then proceeds to discuss the role of a variable gain amplifier in amplifying the signal received by each antenna element of the array, followed by emphasizing the importance of a Low-Noise Amplifier (LNA) in transceiver design to amplify weak signals with minimal noise. In addition, this article provides a detailed discussion on the mixer, which is used to downconvert or upconvert the frequency of the received signal to a more appropriate frequency for further processing or transmission. Finally, the power amplifier (PA), which is used to boost signal power in 5G networks, is also discussed in detail.
IEEE Journal of Solid-State Circuits
This article presents the first 39-GHz phased-array transceiver (TRX) chipset for fifth-generation new radio (5G NR). The proposed transceiver chipset consists of 4 sub-array TRX elements with local-oscillator (LO) phase-shifting architecture and built-in calibration on phase and amplitude. The calibration scheme is proposed to alleviate phase and amplitude mismatch between each sub-array TRX element, especially for a large-array transceiver system in the base station (BS). Based on LO phase-shifting architecture, the transceiver has a 0.04-dB maximum gain variation over the 360 • full tuning range, allowing constant-gain characteristic during phase calibration. A phaseto-digital converter (PDC) and a high-resolution phase-detection mechanism are proposed for highly accurate phase calibration. The built-in calibration has a measured accuracy of 0.08°rms phase error and 0.01-dB rms amplitude error. Moreover, a pseudo-single-balanced mixer is proposed for LO-feedthrough (LOFT) cancellation and sub-array TRX LO-to-LO isolation. The transceiver is fabricated in standard 65-nm CMOS technology with flip-chip packaging. The 8TX-8RX phased-array transceiver module 1-m OTA measurement supports 5G NR 400-MHz 256-QAM OFDMA modulation with −30.0-dB EVM. The 64-element transceiver has a EIRP MAX of 53 dBm. The four-element chip consumes a power of 1.5 W in the TX mode and 0.5 W in the RX mode.