Combined Integer and Floating Point Multiplication Architecture(CIFM) for FPGAs and Its Reversible Logic Implementation (original) (raw)
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FPGA IMPLEMENTATION ON REVERSIBLE FLOATING POINT MULTIPLIER
Field programmable gate arrays (FPGA) are increasingly being used in the high performance and scientific computing community to implement floating-point based system. The reversible single precision floating point multiplier (RSPFPM) requires the design of reversible integer multiplier (2424) based on operand decomposition approach. Reversible logic is used to reduce the power dissipation than classical logic and do not loss the information bit which finds application in low power computing, quantum computing, optical computing, and other emerging computing technologies. Among the reversible logic gates, Peres gate is utilized to design the multiplier since it has lower quantum cost. Operands of the multiplier is decomposed into three partitions of 8 bits each using operand decomposition method. Thus the 2424 bit reversible multiplication is performed through nine reversible 8x8 bit multipliers and output is summed to yield an efficient multiplier optimized in terms of quantum cost, delay, and garbage outputs. This proposed work is designed and developed in the VHSIC hardware description language (VHDL) code and simulation is done using Xilinx 9.1simulation tool.
International Journal of Electrical and Computer Engineering (IJECE), 2023
The reversible logic gates are used to improve the power dissipation in modern computer applications. The floating-point numbers with reversible features are added advantage to performing complex algorithms with highperformance computations. This manuscript implements an efficient reversible floating-point arithmetic (RFPA) unit, and its performance metrics are realized in detail. The RFP adder/subtractor (A/S), RFP multiplier, and RFP divider units are designed as a part of the RFP arithmetic unit. The RFPA unit is designed by considering basic reversible gates. The mantissa part of the RFP multiplier is created using a 24x24 Wallace tree multiplier. In contrast, the reciprocal unit of the RFP divider is designed using Newton Raphson's method. The RFPA unit and its submodules are executed in parallel by utilizing one clock cycle individually. The RFPA unit and its submodules are synthesized separately on the Vivado IDE environment and obtained the implementation results on Artix-7 field programmable gate array (FPGA). The RFPA unit utilizes only 18.44% slice look-up tables (LUTs) by consuming the 0.891 W total power on Artix-7 FPGA. The RFPA unit sub-models are compared with existing approaches with better performance metrics and chip resource utilization improvements.
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Decimal floating point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, scientific, commercial, and financial applications. In this paper we present an IEEE 754-2008 compliant parallel decimal floating-point multiplier designed to exploit the features of Virtex-5 FPGAs. It is an extension to a previously published decimal fixed-point multiplier. The decimal floating-point multiplier implements early estimation of the shift-left amount and efficient decimal rounding. Additionally, it provides all required rounding modes, exception handling, overflow, and gradual underflow. Several pipeline stages can be added to increase throughput. Furthermore, different modifications are analyzed including shifting by means of hard-wired multipliers and delayed carry propagation adders.