Cache Power Optimization Using Multiple Voltage Supplies to Exploit Read/Write Asymmetry (original) (raw)

This paper proposes a novel method to optimize power consumption in cache memory by exploiting the inherent asymmetry in read and write operations in SRAM. By dynamically switching voltage supplies, the method allows cache to operate with a lower voltage during reads while using a higher voltage for writes, thereby significantly reducing overall power consumption without compromising performance. Experimental results confirm the effectiveness of this approach, highlighting substantial power savings in comparison with conventional techniques.