Cache Power Optimization Using Multiple Voltage Supplies to Exploit Read/Write Asymmetry (original) (raw)

Investigation of the Power–Performance Trade-off in High-Performance Processors

Demand for devices that are power-conscious is obvious and growing, and the need for scaling back power dissipation for heat concerns is pressing. However, power does not linearly correspond to performance, and a balance can be achieved. Several design-space changes are considered and evaluated using sim-wattch. In cache design, an effective level 1 cache is an absolute necessity. Leakage power in level 2 cache (and lower levels) can be drastically reduced by transitioning unused blocks to a lowpower state that preserves cache elements; dividing a level 2 cache into superblocks and introducing a buffer of superblocks to keep active can drastically cut leakage power at minimal performance cost. For a baseline configuration, issue width, decode width and RUU size are varied and are found to correspond directly to power consumption. Several branch prediction strategies are tested, showing bimodal to be the most useful, and 2-layer to be the most interesting.

Reducing power in high-performance microprocessors

Proceedings of the 35th annual conference on Design automation conference - DAC '98, 1998

Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each new CPU generation is outstripping the benefits of voltage reduction and feature size scaling. Designers are thus continuously challenged to come up with innovative ways to reduce power, while trying to meet all the other constraints imposed on the design. This paper presents an overview of the issues related to power consumption in the context of Intel CPUs. The main trends that are driving the increased focus on design for low power are described. System and benchmarking issues, and sources of power consumption in a high-performance CPU are briefly described. Techniques that have been tried on real designs in the past are described. The role of CAD tools and their limitations in this domain will also be discussed. In addition, areas that need increased research focus in the future are also pointed out.

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

Journal of Computers, 2009

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas.

Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors

2000

Abstract The ability to estimate power consumption during early-stage definition and trade-off studies is a key new methodology enhancement. Opportunities for saving power can be exposed via microarchitecture-level modeling, particularly through clock-gating and dynamic adaptation. In this paper we describe the approach of using energy-enabled performance simulators in early design. We examine some of the emerging paradigms in processor design and comment on their inherent power-performance characteristics

A Survey of Architectural Techniques For Improving Cache Power Efficiency

Modern processors are using increasingly larger sized on-chip caches. Also, with each CMOS technology generation, there has been a significant increase in their leakage energy consumption. For this reason, cache power management has become a crucial research issue in modern processor design. To address this challenge and also meet the goals of sustainable computing, researchers have proposed several techniques for improving energy efficiency of cache architectures. This paper surveys recent architectural techniques for improving cache power efficiency and also presents a classification of these techniques based on their characteristics. For providing an application perspective, this paper also reviews several real-world processor chips that employ cache energy saving techniques. The aim of this survey is to enable engineers and researchers to get insights into the techniques for improving cache power efficiency and motivate them to invent novel solutions for enabling lowpower operation of caches.

Energy Efficiency in Processors- A Survey

International journal of engineering research and technology, 2018

Energy being consumed in a circuit has been a major concern in the electronic industry and also in Digital System Design. Hence, to reduce the energy consumed by the underlying circuits, CMOS circuits were preferred. With the advancement in the integration technology, more transistors could be fit on the chip. This however led to increase in the energy dissipation. In a computer system, the processors memory and the Disk subsystems are the power hungry units. The numbers of computing systems are increasing drastically and will keep dissipating the energy and thus have an impact on environment too. This paper presents a review of various techniques in energy optimisation at all levels of the processor and hence suggests the ways to optimise the energy along the optimisation metrics associated with each of the technique. KeywordsEnergy, cache, hardware, Dynamic Power, Circuits,

Power and thermal constraints of modern system-on-a-chip computer

Microelectronics Journal, 2015

Power and thermal are major constraints for delivering compute performance in high-end CPU and are expected to be so in the future. For high end processors, junction temperature has been considered the toughest physical constraint that needs to be tightly managed. Recent trends in form-factors and the increased focus on thin and light systems such as Ultra Book, tablet computers and smartphones, shift the challenge away from junction temperature. Ergonomic thermal considerations and power delivery are becoming the limiters for delivering high computational performance density and need to be managed and controlled. In this paper we describe the major physical constraints, design considerations and modern power and thermal management techniques and demonstrate them on an Intel Core(tm) i7 system.

Practical Strategies for Power-Efficient Computing Technologies

Proceedings of the …, 2010

| After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate range, an $ 8Â improvement in power efficiency