A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates (original) (raw)
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Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates
Integration, 2012
In this paper, a new design for low leakage and noise immune wide fan-in domino circuits is presented. The proposed technique uses the difference and the comparison between the leakage current of the OFF transistors and the switching current of the ON transistors of the pull down network to control the PMOS keeper transistor, yielding reduction of the contention between keeper transistor and the pull down network from which previously proposed techniques have suffered. Moreover, using the stacking effect, leakage current is reduced and the performance of the current mirror is improved. Results of simulation in high performance 16 nm predictive technology model (PTM) demonstrate that the proposed circuit exhibits about 39% less power consumption, and nearly 2.57 times improvement in noise immunity with a 41% die area overhead for a 64-bit OR gate compared to a standard domino circuit.
Low power and high performance circuit techniques for high fan-in dynamic gates
SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720), 2004
Domino keeper has to be upsized to keep the noise margin in high fan-in dynamic gates, which increases the power consumption and slows down the evaluation. We propose a four-phase non-full swing keeper design to solve this dilemma. Non-full swing switching at the keeper gate together with alleviated contention help to reduce power consumption and delay. Simulation of 16-input OR gate using 0.13um CMOS SPICE parameters shows that proposed keeper design can reduce power consumption and delay by 26% and 24%, respectively.
IJERT-Robust Low Leakage Controlled Keeper by Current Comparison Domino for Wide Fan in Gates
International Journal of Engineering Research and Technology (IJERT), 2013
https://www.ijert.org/robust-low-leakage-controlled-keeper-by-current-comparison-domino-for-wide-fan-in-gates https://www.ijert.org/research/robust-low-leakage-controlled-keeper-by-current-comparison-domino-for-wide-fan-in-gates-IJERTV2IS120324.pdf A new design for low leakage and noise immune wide fan-in domino circuits is presented. The proposed technique uses the between the leakage current the OFF transistors and the switching current of the ON transistors of the pull down network to control the PMOS keeper transistor, yielding reduction of the contention between keeper transistor and the pull down network from which previously proposed, techniques have suffered. Moreover, using the stacking effect leakage current is reduced and the performance of the current mirror is improved. Results of simulation in high performance 16nm predictive technology model(PTM)demonstrate that the proposed circuit exhibits about 39% less power consumption, and nearly 2.57 times improvement in noise immunity with a 41% die area overhead for a 64-bit OR gate compared to a standard domino circuit. Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. Domino logic circuits with high fan-in are widely used due to their high performance. Scaling down the supply voltage is known to be the most effective way to reduce power consumption. For lower power supply voltage, the threshold voltage of transistors also needs to be scaled down to meet performance requirements. However, the lowering of the threshold voltage leads to an exponential growth of sub threshold leakage current. pull down network (PDN), even when all the inputs are at the low logic level. This leakage is due to the BTBT (band-to-band-tunneling) current, gate tunneling current and the sub threshold current. In addition, voltages of dynamic nodes degrade to zero due to charges haring in the PDN yielding insufficient noise immunity. Use of NMOS transistors in the PDN with relatively high Vth has been proposed as a solution. However, increasing Vth increases the delay of discharging the dynamic node. Another proposed solutions to use a PMOS keeper. However, there is a speed degradation and power loss due to the contention between the pull down network and the strong keeper. Thus, performance of wide dynamic gates is affected by both sub threshold leakage and noise sources. 2 LITERATURE REVIEW Several domino circuits have been proposed in the literature such as HS domino, Split Domino, CKCCD Domino, CKD Domino etc. The main goal of these circuit design techniques is improved noise immunity and circuit performance, especially in wide fan-in circuit.
Noise-Tolerant XOR-Based Conditional Keeper for High Fan-in Dynamic Circuits
2005 IEEE International Symposium on Circuits and Systems
Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits is presented in this paper. Noise immunity is enhanced by conditionally turning on the conditional keepers. The conditional keeper is turned off at some critical moments to reduce the delay and power consumption. The timing of control signals and their effects on noise immunity, power and delay are also examined. High fanin dynamic circuits are used to demonstrate the effectiveness of the conditional keeper on noise immunity. Distributed power gating combined with clock gating design is also examined. All the simulation results are based on TSMC 100nm CMOS technology. Compared to conventional techniques, under the same unity-gain DC noise criteria, more than 20% power reduction and 20% delay reduction are achieved. Under the same delay criteria, more than 1.25X noise immunity improvement is attained. I.
KEEPER DESIGNS FOR WIDE FAN IN DYNAMIC LOGIC
In this era, high performance and multifunctional modules to have in the modern microprocessors has become essential. Dynamic gates have been a brilliant choice in the design of these modules. But, as the length of the devices is reducing drastically, the increasing leakage current and decreasing noise margin in dynamic gates, is affecting the performance of the system and making it less robust. This was overcome by the use of keepers. Using a weak PMOS keeper could solve majority of the problems associated due to contention currents, however with the aggressive scaling technologies this has been rendered less effective. On the other hand, using large PMOS can drastically increase the contention current in wide fan-in dynamic logic which results in a drop in the performance. This paper reviews the issues with traditional keepers, followed by the new keeper techniques coming up, including conditional keeper, leakage replica keeper and adaptive keeper techniques which includes rate sensing keeper & variation tolerant keeper design and discuss each design's limitation. This can help to reduce the contention current, thereby decreasing the leakage power and also minimizing the delay time with an added advantage of reduced noise margins.
A new low-power dynamic circuit for wide fan-in gates
Integration, 2018
In this paper, a new dynamic circuit is proposed to reduce the power consumption of wide fan-in gates. Since the voltage difference across the pull-down network determines the output in the proposed circuit, the voltage swing on the pull-down network can be lowered to decrease the dramatically increasing power consumption of wide fan-in gates. Wide fan-in OR gates are designed and simulated using the proposed domino circuit in 90 nm CMOS technology. Simulation results exhibit up to 2.62X improvement in noise immunity and 44% reduction in power consumption compared to the conventional domino circuits at the same delay. Moreover, a 2-read, 1write ported 64-word × 32-bit/word register file is designed using the proposed domino circuit. The Register file is simulated using low-Vth 90 nm CMOS model in all process corners. The results shows 25% power reduction and 32% speed improvement for the proposed register file in comparison with the conventional register file at the same noise margin floor.
Speeding-up wide-fan in domino logic using a controlled strong PMOS keeper
2008 International Conference on Computer and Communication Engineering, 2008
Wide fan in domino logic finds a variety of applications in microprocessors, digital signal processors, and dynamic memory. Specifically, there is a large number of applications that contain 8 or more transistors connected in parallel in the pull-down network (PDN) and thus the subthreshold leakage and charge sharing become severe. So, a strong PMOS keeper must be used in order to compensate for this leakage. However, the use of a strong keeper in the conventional domino circuit degrades the speed of the circuit considerably or results in an erroneous output. In this paper, a novel technique that acts to speed up the operation of wide fan in domino logic using a properly sized keeper is proposed. The keeper is controlled via a controlling CMOS circuit. Some design issues of this technique such as the effect of the charge sharing on the operation of the proposed circuit and the size of the PMOS keeper will be discussed in this paper. Simulation will be carried out for the 0.13 µm technology with V DD =1.2 V for the case of 16 NMOS transistors in the PDN. Simulation results show the better noise immunity of the proposed circuit and the larger speed, however at the cost of increasing the area.
Integration, the VLSI Journal, 2015
In this paper, a new leakage-tolerant domino circuit is presented which has lower power consumption and higher noise immunity without significant delay increment for wide fan-in gates. The main idea in the proposed circuit is using sense amplifier for sensing the difference between voltages across the pull down network (PDN). This strategy provides correct output. In the proposed technique, therefore, the voltage swing of the dynamic node can be reduced to decrease the power consumption caused by the heavy switching capacitance in wide fan-in gates. The simulation is provided with 64-bit wide OR gates using a 90 nm CMOS technology model. The simulation results are compared with that of standard domino circuits at the same delay, and 35% power consumption reduction and 2.31 Â noise-immunity improvement are observed.
An Improved Noise-Tolerant Domino Logic Circuit for High Fan-in Gates
2005
Dynamic logic circuits are used for high performance circuits. Wide OR gates are employed for high speed processors, DRAM, SRAM and high speed logic circuits. Dynamic logic circuits are used for their high performance, but their high noise and extensive leakage has caused some problems for these circuits. However, dynamic CMOS circuits are inherently less resistant to noise than static CMOS gates. So, for dynamic CMOS, the first improvement has to be noise tolerance for the overall reliable operation of VLSI chips designed using deep submicron process technology. In this paper, we propose a new domino logic circuit scheme to reduce subthreshold leakage current in standby mode and to improve noise immunity for wide OR gates. The conditions for our simulations are: Berkeley CMOS 70nm predictive technology for simulated results [1], 0.9V power supply and bottleneck operating temperature of 110°C. Simulation results on 8, 16, 32 and 64 inputs OR gates showed improvements from 2.116X to 15.83X compared with other conventional techniques. Furthermore, while there is an area overhead of 13% compared with 8-input FLSDL, we have achieved a decreased area of 5%, 23% and 33% compared with 16, 32, and 64-input footless standard domino logic (FLSDL) respectively.
2013 IEEE CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGIES, 2013
Domino CMOS logic circuits are widely used these days in the design of high-performance modules in modern day integrated chips and microprocessors. The feature of high speed and less area overhead of these logic circuits compared to other logic styles make them a popular choice in the design of high speed circuits. As power consumption is directly proportional to the dynamic node capacitance, a new circuit technique is presented in this paper which employs the partitioning of dynamic node capacitance with the help of a splitter transistor to reduce the power consumption. With the help of a modified keeper circuitry, the contention between keeper and the pull down evaluation network is reduced drastically. Simulation results show a reduction of 78.91 % when compared to the Conditional Keeper (CKP) technique and reduction by 65.51 % when compared with the Adaptive Pseudo Dual Keeper (APDK) scheme. The reduction is about 83.56 % when compared to CKP and 70.27 % when pitted against the APDK when the issue of contention current is taken up. The reduction in power and contention current is found to be true when the design concept was tested for a 32 bit comparator circuitry. Simulations have been performed using the SILVACO EDA tool on a 32-bit wide fan-in OR gate in 32nm process technology at a frequency of 1.5 GHz and supply voltage of 0.9V. Monte Carlo simulations have also been performed to test an idea which makes the circuit tolerant to process variations.