A Novel Low Power 8-Bit Binary Weighted Charge Steering DAC with Integrated Power Supply using CMOS (original) (raw)

A 130-NM CMOS 400 MHZ 8-Bit Low Power Binary Weighted Current Steering DAC

International Journal on Cybernetics & Informatics, 2016

A low power low voltage 8-bit Digital to Analog Converter consisting of different current sources in binary weighted array architecture is designed. The weights of current sources are depending on the binary weights of the bits. This current steering DAC is suitable for high speed applications. The proposed DAC in this paper has DNL, INL of ±0.04, ±0.05 respectively and the power consumption of 16.67mw. This binary array architecture is implemented in CMOS 0.13µm 1P2M technology has good performances in DNL, INL and area compared with other researches.

Design and implementation of 4 bit binary weighted current steering DAC

International Journal of Electrical and Computer Engineering (IJECE), 2020

A compact current-mode Digital-to-Analog converter (DAC) suitable for biomedical application is repesented in this paper .The designed DAC is binary weighted in 180nm CMOS technology with 1.8V supply voltage. In this implementation, authors have focused on calculaton of Non linearity error say INL and DNL for 4 bit DAC having various type of switches: NMOS, PMOS and Transmission Gate. The implemented DAC uses lower area and power compared to unary architecture due to absence of digital decoders. The desired value of Integrated non linearity (INL) and Differential non linearity (DNL) for DAC for are within a range of +0.5LSB. Result obtained in this works for INL and DNL for the case DAC using Transmission Gate is +0.34LSB and +0.38 LSB respectively with 22mW power dissipation.

Low power designs of current steered DACs in CMOS process: A review

International Journal on Electrical Engineering and Informatics

Low power design has become popular nowadays because ofdevelopment of improveddata converters with high resolution in CMOS process. Electronic device manufacturersare competing each other to produce devices that can extend battery life, have inexpensive packaging and cooling systems as well as reduce the size.The objective of this paper is to review various low power designs in digital to analog converters (DAC). The methods used to reduce the power consumption are presented in details. We focused the designs in the segmentation current steering DACs, as most of the low power designs illustarted in literatures are based on this architecture. From this review, we find that triple segmented architectureand spike free switching can reduce the power consumption effectively. This review paper can be a reference for the researchers and engineers to develop low power CMOS DACsfor various applications.

A 15-bit binary-weighted current-steering DAC with ordered element matching

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Device variability has become one of the fundamental challenges to high-resolution and high-accuracy DACs in nanometer and emerging processes. This paper introduces a 15bit binary-weighted current-steering DAC in a standard 130nm CMOS technology, which utilizes a new random mismatch compensation theory called ordered element matching to improve the static linearity performance with the presence of large variability. The chip's core area is less than 0.42mm 2 , among which the 7-bit MSB current source area is well within 0.021mm 2 . Measurement results have shown that the DAC's DNL and INL can be reduced from 9.85LSB and 17.41LSB to 0.34LSB and 0.77LSB, respectively.

CMOS current-steering DAC architectures based on the triple-tail cell

International Journal of Circuit Theory and Applications, 2008

In this paper two novel current-steering digital-to-analog converter (DAC) architectures, exploiting the triple-tail cell as switching element, are presented. The proposed solutions are theoretically analysed and design equations are carried out. The two architectures show better performance than the classical binary-weighted solution and it is shown that they can profitably substitute the binary sub-DAC section in a segmented topology. Theoretical results are compared with behavioural-level simulations and confirm the effectiveness of the proposed architectures.

A Novel Architecture for Current-Steering Digital to Analog Converters

Proceedings of the International Conference on Advances in Computer Science and Electronics Engineering, 2012

This paper presents a novel Current Steering Digital to Analog Converter architecture to reduce area as well as power dissipation. The current cells of conventional binary weighted architecture require larger size of transistors for MSBs. In this paper, same sized current cell transistors for MSBs as that of LSBs and a current mirror circuit is used between the load and MSBs to provide necessary higher current. Here, 6-bit CS-DAC is simulated. The area of this proposed CS-DAC has decreased by about 12% and power dissipation by about 50% in comparison with a conventional Binary architecture.

COMPARATIVE STUDY OF CURRENT STEERING DAC BASED ON IMPLEMENTATION USING VARIOUS TYPES OF SWITCHES

IAEME Publication, 2020

Digital to Analog Converter (DAC) is a circuit known as a circuit of all seasons. It has wide applications in various fields. Current steering has an advantages over others are in form its speed and power consumption. Non linearity error-Integrated non Linearity (INL) & Differential Non Linearity (DNL) are one of the important measure for DAC and having great impact on the performance of DAC used specifically in the field of medical. Amount of INL and DNL depends on the type of architecture say binary weighted, unary weighted or segmented DAC. Types of switching also have great impact on the INL and DNL. This article presents design and implementation of segmented DAC using various switches like NMOS, PMOS, Transmission Gate and differential switch. The concept of segmented offered the advantage in form of reduction in glitches compared to binary weighted DAC. Looking to Comparison of all, Results of DAC using Differential switch offered an advantage in from of uniform step size on output. Eventually that results in form of better INL and DNL. In order to simulate the design, cadence virtuoso tool with 180 nm MOS technology is used.

A 14-bit dual current-steering DAC

2004

ABSTRACT A 14-bit dual current-steering digital-to-analog converter implemented in a 0.25 µm CMOS process is presented in this work. Both implementation issues and measurement results are presented. The measured spurious-free dynamic range is higher than 73 dB for signal frequencies up to 3 MHz, and a measured multi-tone power ratio of approximately 71 dB is reported for an ADSL-like input.

An ultra low-power DAC with fixed output common mode voltage

AEU - International Journal of Electronics and Communications, 2018

A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (V cm) of the DAC remains fixed for all the digital codes. This feature helps a lot to improve the linearity of a typical SAR ADC and reduce the power consumption of comparator. The layout of the proposed DAC is very simple and easy to extend in contrast to the binary weighted CDACs where the layout needs lots of care and time. Several Monte-Carlo and Post-Layout simulations using CMOS 0.18 technology prove the benefits of the proposed CDAC. The proposed CDAC reduces the power consumption by 99.8% while enhances the speed and linearity of the comparator in a SAR ADC.

Low Power And High Performance Current Steering DAC Using Different GDI Logics

The current steering digital-to-analog converters (DAC) carry out a vital role in data-processing systems like communication systems. Digital-to-analog (DAC) converters used in modern communication systems mainly for linearity, effectiveness, and for high speed applications. The segmented approach of DAC in proposed work is mainly used for minimizing power dissipation, chip area. In general DAC have a tendency to operate at high rate of sampling, the current switches will affect the output with glitches because the transitions made at high sampling rate. In digital-to-analog converters decoders are designed with conventional CMOS logic, which are having more power dissipation, chip area than the proposed Gate Diffusion (GDI) Input logics. In this paper to minimize the power dissipation of decoder circuit in DAC, binary-thermometer decoder is implemented with GDI, Full-swing (FSGDI) and Transmission (TSGDI) logics. This method has been successfully shown for 8-bit 500-MHz segmented-current steering DAC having a less number of transistors, which results in low power dissipation.