A Reduced-Area, Low-Power CMOS Bandgap Reference Circuit (original) (raw)

2007 IEEE International Symposium on Circuits and Systems, 2007

Abstract

This paper presents a low-voltage, reduced-area CMOS bandgap reference (BGR) circuit for low-power applications. Significant area reduction is achieved by utilizing a resistive T-network in combination with layout-efficient opamp compensation. A complete analysis, including the dual-loop stability, reveals several tradeoffs between area, loop-gain, stability and offset sensitivity. Based on this analysis, a high-performance design, in a 0.18mum CMOS process, is

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