A proposed synthesis method for Application-Specific Instruction Set Processors (original) (raw)

Design requirements for embedded systems call for architectures with small size, low power consumption and low cost. These requirements can be met by designing custom architectures for every single application. However, the commercial viability of embedded systems calls for short design cycles. These requirements are conflicting: custom architectures take a long time and substantial effort to produce, because of the need to manually generate design evaluation tools, such as simulators and compilers, for each architecture candidate. This conflict can be eliminated by providing a system capable of generating all design evaluation tools for a given candidate architecture. This thesis presents two components of the ARIES environment for architecture synthesis: the machine description language ISDL and the G ENSIM simulator generator system. We also briefly describe the H GEN hardware model generator. In the ARIES system, candidate architectures are described in the ISDL language. From t...