Enhanced Acquisition and Tracking in All Digital Phase-Locked Loops (original) (raw)

This paper presents a technique to substantially mitigate the tracking jitter of all digital phase-locked loops and, hence, enhance the overall performance of the loop. This has been achieved by a structure utilizing a notch f ilter in a cascade arrangement with the loop f ilter to suppress the undesired frequency components and preserve the DC value at the output of the loop f ilter, which represents the trial value of the carrier phase error. A rapid acquisition of the error and a bit error rate (BER) performance close to theoretical results have been achieved.