Enhanced Acquisition and Tracking in All Digital Phase-Locked Loops (original) (raw)

Digital phase-locked loop and its realization

The realization of a digital phase-locked loop (DPLL) requires to choose a suitable phase detector and to design an appropriate loop filter; these tasks are commonly nontrivial in most applications. In this paper, the DPLL system is first formulated as a state estimation problem; then an extended Kalman filter (EKF) is applied to realize this DPLL for estimating the sampling phase. Therefore, the phase detector and loop filter are simply realized by the EKF. The proposed DPLL has a simple structure and low realization complexity. Computer simulations for a conventional DPLL system are given to compare with those for the proposed timing recovery system. Simulation results indicate that the proposed realization can estimate the input phase rapidly without causing a large jittering.

Optimized Design of Digital Phase Locked Loops for RF Carrier Acquisition.

International Journal of Engineering Sciences & Research Technology, 2014

This paper presents optimized implementation of Digital Phase Locked Loops (DPLL) for generating RF carrier signal used for phase demodulation. The method used for designing DPLL is based on linear control theory and the receiver is phase locked at higher radio frequency signal which is highly noisy. The building blocks of DPLL such as loop filter are implemented with a new method in digital domain for better noise rejection and accuracy. The paper aims to offer aided acquisition of RF signal with fast frequency and phase locking. The designed DPLL is used for higher frequency range applications of the order of GHz and theoretically expected frequency response graph of the filter is verified practically. HDL programming language is used for coding and simulation.

A survey of digital phase-locked loops

Proceedings of The IEEE, 1981

All digital components were clocked synchronously by a common 1.097 MHz reference. Since then, the DPLL field has cuits, e.g., lock detection and automatic gain contrd [Z]. 'In practice, thii circuit is usually augmented by other contrd cir-0018-9219/81/04004410$00.75 0 1981 IEEE LINDSEY AND CHIE: DIGITAL PHASE-LOCKED LOOPS 411

Jitter minimization in Digital Transmission using dual phase locked loops

2005 International Conference on Microelectronics

Timing jitter is a concern in high frequency timing circuits. Its presence can degrade system performance in many high-speed applications. In this paper, a new method for minimization of timing jitter due to phase locked loops is described. The timing jitter can be minimized using two phase locked loops connected in cascade, where the first one has Voltage Controlled crystal

A Fast-Locking Digital Phase-Locked Loop

Third International Conference on Information Technology: New Generations (ITNG'06), 2006

A conventional digital phase-locked loop (DPLL) is designed using [1] to operate at 1GHz using 0.18 µm CMOS technology; its lock time is 4.19µs. By adding a coarse/fine tuning control unit composed of a digital-to-analog converter (DAC) and a counter as well as switching the currents of the charge pump, a fast-locking DPLL results, with a lock time of 1.02 us, i.e. an improvement by a factor of 4. Simulations for both DPLLs verified the performance improvement due to using a fast-locking technique.

Phase Locked Loop Design for Fast Phase and Frequency Acquisition

The specific property of fast locking of PLL is required in many clock and data recovery circuits. The most versatile application of the phase locked loops (PLL) is for clock generation and clock recovery in microprocessor, networking, communication systems, and frequency synthesizers. Phase locked-loops (PLLs) are commonly used to generate well-timed on-chip clocks in high performance digital systems. Modern wireless communication systems employ Phase Locked Loop (PLL) mainly for synchronization, clock synthesis, skew and jitter reduction. Because of the increase in the speed of the circuit operation, there is a need of a PLL circuit with faster locking ability. Hence there is a necessity of a PLL which must operate in the GHz range with less lock time. This paper presented a PLL with redesigning of individual blocks. The PLL is designed using 180 nm CMOS technology for high performance with 1.8 V power supply. Keywords-Phase Locked Loop (PLL), Phase Frequency Detector (PFD), Charge Pump (CP), Low Pass Filter (LPF), Voltage Controlled Oscillator (VCO)

DESIGN OF ALL DIGITAL PHASE LOCKED LOOP (D-PLL) WITH FAST ACQUISITION TIME

A Digital PLL is designed with improved acquisition time and power efficiency. The implemented D-PLL can operate from 6.54MHz to 105MHz with a power dissipation of is 7.763µW (at 210MHz) with 1.2V supply voltage. The D-PLL is synthesized using cadence RTL compiler in 45nm CMOS process technology.

Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops

IEEE Transactions on Circuits and Systems I: Regular Papers, 2013

This paper discusses novel architectures and circuit techniques for DPLLs. These include: methods to have a wide temperature range in the digitally controlled oscillator (DCO) for ring-oscillator based DPLLs, re-circulating time to digital converter (TDC) architecture to support a large input phase error range, efficient, modular, divider architectures that provide 50% output duty cycle, while allowing dynamic programmability of the division ratio, and fractional DPLL approaches for spur cancellation and low power operation. The techniques described in the paper have been used to build DPLLs for serializer-deserializer (SerDes), processor clock generation, and wireless connectivity applications in 65 nm and 45 nm CMOS. These implementations are briefly discussed and representative silicon results are presented. Index Terms-Digital phase lock loops, phase lock loops. I. INTRODUCTION P HASE LOCK loops (PLLs) are widely used in today's systems-on-chip (SOCs) to perform various functions that include clock generation for A/D and D/A converters and digital processors, for clock and data recovery (CDR) in data serializers and as local oscillators (LO) in RF transceivers. Multiple instances of PLLs are used in a typical SOC. Until recently, a vast majority of PLLs have been based on the traditional charge-pump architecture shown in Fig. 1. Here, divided versions of an input reference clock and the output of a voltage controlled oscillator (VCO) are compared in a phase frequency detector (PFD), which in conjunction with a charge pump and a low pass loop filter generates a control signal for the VCO. This results in a phase and frequency lock between RE-FCLK and FBCLK, making frequency of CLKOUT equal to times the reference frequency FREF. Thus, the output Manuscript

Minimization of Jitter in Digital Systems using Dual Phase-locked Loops

2013

Timing jitter is a concern in high frequency timing circuits. Its presence can degrade system performance in many high-speed applications. This paper describes a new method for minimization of timing jitter using two phase-locked loops connected in cascade, where the first one has a voltage-controlled crystal oscillator to eliminate the input jitter and the second is a wide-band phase-locked loop. RMS jitter, the usual system performance criterion, is analyzed in both phase-locked loops, and results of simulations using MATLAB are presented. The methodology described is also applicable to other types of clock generator.