Design and Performance Analysis of Various Adders and Multipliers Using GDI Technique (original) (raw)

High Speed Adder Using Gdi Technique

International Journal of Engineering Technologies and Management Research, 2020

Full adder is an important component for designing a processor. As the complexity of the circuit increases, the speed of operation becomes a major concern. Nowadays there are various architectures that exist for full adders. In this paper we will discuss about designing a low power and high speed full adder using Gate Diffusion Input technique. GDI is one of the present day methods through which one can design logical circuits. This technique will reduce power consumption, propagation delay, and area of digital circuits as well as maintain low complexity of logic design. The performance of the proposed design is compared with the contemporary full adder designs.

IJERT-An Efficient Advanced High Speed Full-Adder Using Modified GDI Technique

International Journal of Engineering Research and Technology (IJERT), 2013

https://www.ijert.org/an-efficient-advanced-high-speed-full-adder-using-modified-gdi-technique https://www.ijert.org/research/an-efficient-advanced-high-speed-full-adder-using-modified-gdi-technique-IJERTV2IS120151.pdf In this paper, high performance full adder circuit is proposed. A full-adder is one of the essential components in the designing of digital circuit, many improvements have been made to reduce the architecture of a full-adder. The proposed method for designing a one bit full adder aims on GDI(Gate Diffusion Input). Analysis is based on some simulation parameters like number of transistors, power, delay, power delay product of the digital circuit. The proposed full adder using GDI technique used to reduce the power up to 0.135nw .