Design of Five Stage Pipelined Microprocessor with a 16K Cache Memory (original) (raw)

Pipelining is a technique in which several instructions are overlapped. With this technique we can achieve a better system throughput. In this work, a five stage microprocessor is designed without interlocked pipelined stages with a 16K cache memory. MIPS (Microprocessor with Interlocked Pipeline Stages) has a 32 bit architecture with instructions of 32 bit and thirty two, 32 bit general purpose registers. Also, a cache memory is designed with a size of 16K having direct mapped configuration. The cache has four blocks, each of 4K memory size. The fundamental purpose of cache memory is to store instructions that are regularly used by the processor during the execution of program instructions. Pipelining includes subdividing the system into different stages. Each stage has buffers in between them. Here it is divided into five stages, instruction fetch stage (IF), instruction decode stage (ID), instruction execute stage (EX), memory stage (MEM) and write-back stage (WB). Each stage imp...