Low Power Analog Design in Scaled Technologies (original) (raw)
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Scaling of Low Power CMOS Circuits with Optimum Performance
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In recent years, increasing demand for portable devices has made low power consumption a main design consideration. This paper optimizes the CMOS basic cells based on a simulation procedure to analyze how three aspects of IC power consumption, i.e. dynamic power, leakage power and peak power, can be considered together in optimizing the sizing and design of basic cells without a reduced degradation in performance with scaled supply voltage. The study was performed using basic cells in 32nm process technology for 1.8V to sub-1V by exploiting the linear dependency of supply voltage V DD and width of transistor W with circuit switching delay and power consumption. The optimization was carried out with 256-bit CMOS carry-ripple adder and 8-bit CMOS Braun multiplier as test vehicles. It is the aim of this paper to adopt a systematic approach to optimize CMOS basic cells with the use of RC delay modeling technique and geometry scaling to achieve optimum performance for low voltage adv...
Design principles for low-voltage low-power analog integrated circuits
Analog Integrated Circuits and Signal Processing, 1995
In this paper it is argued that there are good reasons to choose current as the information-carrying quantity in the case of low-voltage low-power design constraints. This paper focuses on the influence of the transfer quality on that choice. To obtain power-efficient transfer quality, indirect feedback is shown to be a good alternative to traditional feedback techniques.
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Journal of Electrical Engineering, 2017
In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.
Technology Scaling and Low Power Design Techniques
Scaling the feature size of transistor made a remarkable advancement in silicon industry. The demand for power-sensitive design has grown significantly in recent years due to growth in portable applications. The need for power-efficient design techniques is increasing. Various efficient design techniques have been proposed to reduce both dynamic as well as static power in state-of-the-art VLSI applications. In this paper, different circuit design techniques both static and dynamic are discussed that reduce the power consumption.
Solid-State Circuits, …, 1992
Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining coniputational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architectural-based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption.
Supply and threshold voltage scaling for low power CMOS
IEEE Journal of Solid-state Circuits, 1997
This paper investigates the effect of lowering the supply and threshold voltages on the energy efficiency of CMOS circuits. Using a first-order model of the energy and delay of a CMOS circuit, we show that lowering the supply and threshold voltage is generally advantageous, especially when the transistors are velocity saturated and the nodes have a high activity factor. In fact, for modern submicron technologies, this simple analysis suggests optimal energy efficiency at supply voltages under 0.5 V. Other process and circuit parameters have almost no effect on this optimal operating point. If there is some uncertainty in the value of the threshold or supply voltage, however, the power advantage of this very low voltage operation diminishes. Therefore, unless active feedback is used to control the uncertainty, in the future the supply and threshold voltage will not decrease drastically, but rather will continue to scale down to maintain constant electric fields.
Designing low-power digital CMOS
Electronics & Communication Engineering Journal, 1994
The increasing levels of circuit integration are leading to the implementation of highly sophisticated algorithms. Many of the commercial application areas have a requirement for portability which leads to the need for low-power design. This article considers the issues and design solutions for complex low-power digital CMOS IC design.
A survey of non-conventional techniques for low-voltage low-power analog circuit design
Designing integrated circuits able to work under low-voltage (LV) low-power (LP) condition is currently undergoing a very considerable boom. Reducing voltage supply and power consumption of integrated circuits is crucial factor since in general it ensures the device reliability, prevents overheating of the circuits and in particular prolongs the operation period for battery powered devices. Recently, non-conventional techniques i.e. bulkdriven (BD), floating-gate (FG) and quasi-floating-gate (QFG) techniques have been proposed as powerful ways to reduce the design complexity and push the voltage supply towards threshold voltage of the MOS transistors (MOST). Therefore, this paper presents the operation principle, the advantages and disadvantages of each of these techniques, enabling circuit designers to choose the proper design technique based on application requirements. As an example of application three operational transconductance amplifiers (OTA) based on these non-conventional techniques are presented, the voltage supply is only ±0.4 V and the power consumption is 23.5 μW. PSpice simulation results using the 0.18 μm CMOS technology from TSMC are included to verify the design functionality and correspondence with theory.
Low-power CMOS with subvolt supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000
We first present a circuit taxonomy along the space and time dimensions, which is useful for classifying generic low-power techniques, followed by an analysis of optimal power supply and threshold voltages and transistor sizing for minimizing the energy-delay product of a class of complementary metal-oxide-semiconductor (CMOS) digital circuits. Index Terms-Digital-complementary metal-oxide-semiconductor (CMOS) VLSI, low-power design, low voltage, power consumption model.