Time Properties Verification Framework for UML-MARTE Safety Critical Real-Time Systems (original) (raw)

Time properties verification of UML/MARTE real-time systems

Proceedings of the 2014 IEEE 15th International Conference on Information Reuse and Integration (IEEE IRI 2014), 2014

UML and MARTE are standardized modeling languages widely used in industry for the design of realtime systems. However, formal verification at early phases of the system lifecycle for UML/MARTE models remains an open issue mainly for dependability features. In this paper, we show how we can provide a formal verification of time properties from a UML/MARTE description. For this, we translate this latter description expressed (Timed Computation Tree Logic). We illustrate the proposed approach on a case study derived from a real-time asynchronous system (Integrated Modular Avionics (IMA)-based airborne system).

Temporal Properties Veri�cation of Real-Time Systems Using UML/MARTE/OCL-RT

Dependability is a key feature of critical Real-Time Systems (RTS). In fact, errors may lead to disastrous consequences on life beings and economy. To ensure the absence or avoidance of such errors, it is important to focus on RTS veri�cation as early as possible. As MARTE UML pro�le is the standard de facto for modelling RTS, we suggest to ex- tend UML diagrams by a formal veri�cation stage. More precisely, in the �rst part we propose a transformation approach of Interaction Overview Diagrams and Timing Diagram merged with UML-MARTE annotations into Time Petri Nets (TPN) models Then, in the second part, we show how we can derive Timed Computational Tree Logic formulae from Ob- ject Constraint Language-Real Time (OCL-RT) constraints. This formal veri�cation is performed by the Romeo model-checker. Finally, we illus- trate our approach through a case study derived from a RT asynchronous system (Integrated Modular Avionics/based airborne system).

Formal Verification of UML MARTE Specifications Based on a True Concurrency Real Time Model

Comput. Informatics, 2020

For critical embedded systems the formal validation and verification is required. However, the real-time model checking suffers from problems of statespace explosion and clock explosion. The aim of this paper is to ensure an improvement of the Modeling and Analysis of Real-Time Embedded systems (MARTE), which is de facto standard, with formal semantics for verification finality. Therefore, we propose an operational method for translating UML sequence diagrams with MARTE annotations to Time Petri nets with Action Duration specifications (DTPN). Based on true concurrency semantics, the semantics of these specifications are defined in terms of Duration Action Timed Automata (daTA). Formal Verification of UML MARTE Based on a Real Time Model 1023

Formal Verification of UML2 Timing Diagrams based on Time Petri Nets

International Journal of Information Systems in the Service Sector, 2016

Unified Modeling Language (UML) is using in the design notation in industry and academia projects. Interesting by the critical Real-Time System verification, it is important to ensure its dependability in order to avoid eventual errors. In this paper, the authors aim to extend the UML diagrams by adding a formal verification stage. They tackle with the UML2 timing diagram (TD), as interaction diagram in order to describe the system's behavior in temporal way. For that, the authors give a formal description for TD using Time Petri Nets (TPN). Then, they propose a formal verification by means of Romeo Model Checker. In particular, they show how to formulate quantitative properties using TCTL (timed computation tree logic). In addition, the authors show how they can derive the TCTL formulae from Object Constraint Language-Real Time (OCLRT) constraints. Finally, they illustrate the proposed approach through a real case study.

Formal and efficient verification techniques for Real-Time UML models

The real-time UML profile TURTLE has a formal semantics expressed by translation into a timed process algebra: RT-LOTOS. RTL, the formal verification tool developed for RT-LOTOS, was first used to check TURTLE models against design errors. This paper opens new avenues for TURTLE model verification. It shows how recent work on translating RT-LOTOS specifications into Time Petri net model may be applied to TURTLE. RT-LOTOS to TPN translation patterns are presented. Their formal proof is the subject of another paper. These patterns have been implemented in a RT-LOTOS to TPN translator which has been interfaced with TINA, a Time Petri Net Analyzer which implements several reachability analysis procedures depending on the class of property to be verified. The paper illustrates the benefits of the TURTLE RT-LOTOS TPN transformation chain on an avionic case study.

STVR 2010 - Verification of real-time systems design

The main objective of this paper is to present an approach to accomplish verification in the early design phases of a system, which allows us to make the system verification easier, specifically for those systems with timing restrictions. For this purpose we use RT-UML sequence diagrams in the design phase and we translate these diagrams into timed automata for performing the verification by using model checking techniques. Specifically, we use the Object Management Group's UML Profile for Schedulability, Performance, and Time and from the specifications written using this profile we obtain the corresponding timed automata. The 'RT-UML Profile' is used in conjunction with a very well-known tool to perform validation and verification of the timing needs, namely, the UPPAAL tool, which is used to simulate and analyze the behaviour of real-time dynamic systems described by timed automata.

Some issues in real-time systems verification using time Petri Nets

Journal of the Brazilian Society of Mechanical Sciences and Engineering, 2011

Time Petri Net (TPN) models have been widely used to the specification and verification of real-time systems. However, the claim that most of these techniques are useful for realtime system verification can be discussed, based on two assumptions: i) to be suitable for real-time systems verification, a technique must be able to check timing properties, both safe and behavioral, and ii) the underlying algorithm must be efficient enough to be applied to complex systems design. In this paper we will discuss the suitability of commonly accepted verification techniques that use model-checking as a verification framework and TPN as a description model. We present a new algorithmic approach that allows computation of end-to-end time between activities over an abstract state space model. The proposed approach needs to compute the abstract state space only once improving the efficiency of the verification process and turning it suitable for large problems. We also introduce a new sufficient condition for abstract states space to preserve the branching time properties that yields more compact graphs than the condition already used in actual approaches. The approach would fit a design environment also based on Petri Nets called GHENeSys (General Hierarchical Enhanced Petri Nets). The results obtained, using our verification approach are compared with similar available approaches.

Reachability analysis of real-time systems using time Petri nets

IEEE Transactions on Systems, Man and Cybernetics, Part B (Cybernetics), 2000

Time Petri nets (TPNs) are a popular Petri net model for specification and verification of real-time systems. A fundamental and most widely applied method for analyzing Petri nets is reachability analysis. The existing technique for reachability analysis of TPNs, however, is not suitable for timing property verification because one cannot derive end-to-end delay in task execution, an important issue for time-critical systems, from the reachability tree constructed using the technique. In this paper, we present a new reachability based analysis technique for TPNs for timing property analysis and verification that effectively addresses the problem. Our technique is based on a concept called clock-stamped state class (CS-class). With the reachability tree generated based on CS-classes, we can directly compute the end-to-end time delay in task execution. Moreover, a CS-class can be uniquely mapped to a traditional state class based on which the conventional reachability tree is constructed. Therefore, our CS-class-based analysis technique is more general than the existing technique. We show how to apply this technique to timing property verification of the TPN model of a command and control (C2) system. Index Terms-Reachability analysis, real-time systems, real-time verification, time Petri nets. I. INTRODUCTION A REAL-TIME system is one whose logical correctness is based both on the correctness of the outputs and on their timeliness [8], [10]. It must satisfy explicit (bounded) response-time constraints or risk severe consequences, including system failure. Consequently, a key requirement to real-time systems is the end-to-end delay in task execution, a critical issue in the design and analysis of these time critical systems [9], [14], [15]. This paper aims to address the timing property analysis and verification of real-time systems. Real-time systems, such as aircraft navigation, command and control, and power plant monitoring systems, are often reactive or embedded control systems that must constantly react to their environment and interact among components within the systems. Consequently, concurrency, resource sharing, synchronization, and deadlock resolution are among essential issues

Improving the Verification of Real-Time Systems Using Time Petri Nets

Journal of Control, Automation and Electrical Systems, 2017

Formal verification methods using Time Petri Net have called the attention of researchers and practitioners in real-time systems design during the last two decades. Special attention was dedicated to methods that could be integrated to the design process since the very beginning, that is, in the requirement phase. However, real-time systems requirements are always concerned with quantitative temporal properties, and therefore, a verification technique should give some feedback on target values for these properties. This paper presents an alternative algorithm-based on reachability-to treat the real-time verification of discrete systems. The proposed method is based on an enumerative technique to generate the complete state space that has some advantages-since it has to be done only once-and disadvantages-since the process is combinatorial. However, our proposal leads to better results when compared to other available techniques, especially to complex problems, besides being able to evaluate quantitative and qualitative properties in the same process. Timed Computation Tree Logic is used as specification language, and Timed Transition Graph (TTG) is introduced to represent system functional behavior. A new algorithm is proposed to build a TTG and applied to a case study to illustrates the operation of the proposed algorithm.

Verification of real-time embedded systems using Petri net models and timed automata

2002

There is a lack of new verification methods that overcome the limitations of traditional validation techniques and are, at the same time, suitable for real-time embedded systems. This paper presents an approach to formal verification of real-time embedded systems modeled in a timed Petri net representation. We translate the Petri net model into timed automata and use model checking to prove whether certain properties hold with respect to the system model. We propose two strategies to improve the efficiency of verification. First, we apply correctness-preserving transformations to the system model in order to obtain a simpler, yet semantically equivalent, one. Second, we exploit the structure of the system model by extracting its the sequential behavior. Experimental results demonstrate significant improvements in the efficiency of verification. This research has been sponsored by the Swedish Agency for Innovation Systems (VINNOVA) in the frame of the SAVE project.