Performance optimization of MOS current-mode logic (original) (raw)

2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), 2016

Abstract

The MOS current-mode logic (MCML) family is suitable for high-frequency applications due to the use of a static current source, thus relatively stabilizing its power consumption. However, there are various tradeoffs in the design of this family due to the contradictions that arise when choosing values for the load resistance or the current-source strength. In this paper, the performance of the MCML family will be investigated by using a figure of merit. The performance metrics will be derived in terms of the design parameters and the values of these parameters that correspond to the optimum performance will be estimated (if found). The analysis will be verified by comparison with the simulation results adopting the 45 nm CMOS technology.

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