Timing analysis in high-level synthesis (original) (raw)

Timing Models for High-Level Synthesis

Proceedings of the conference …, 1992

In this paper, we describe a timing model for clock estimation during high-level synthesis. In order to obtain realistic timing estimates, the proposed model considers all delay elements, including datapath, control and wire delays, and several technology factors, such as layout architecture, technology mapping, buffers insertion and loading effects. The experimental results show that this model can provide much better estimates than previous models. This model is well suited for automatic and interactive synthesis as well as feedback-driven synthesis where performance matrices must be rapidly and incrementally calculated. List of Figures 1 Wire: (a) RT model, (b) equivalent RC delay model. 4

Timing Analysis in a Logic Synthesis Environment

A goal of a logic synthesis system is the automatic generation of area optimised designs that meet timing requirements. The desi n process involves repeated timing analyses followed % y appropriate modifications. We present fast new algorithms for system level timing analysis and for the generation of timing constraints to guide the redesign of portions of combinational logic. Our systematic approach correctly models designs that incorporate level sensitive latches controlled by multifrequency, as well as simple multi-phase, clocks. A new feature is that the minimum number of settling times are evaluated for the nodes of combinational networks with input transitions controlled by different clock signals. The computer program Hummingbird uses the algorithms presented. Hummingbird interfaces with other programs in the Berkeley Synthesis System through the OCT data base. For a digital signal processing chip, comprising 3681 standard cells, timing analysis is performed in 14.87 cpu seconds on a VAX 8800 running the ULTRIX operating system.

High-level synthesis with behavioral level multi-cycle path analysis

High-level synthesis (HLS) tools generate register transfer level (RTL) hardware descriptions through a process of resource allocation, scheduling and binding. Intuitively, RTL quality influences the logic synthesis quality. Specifically, the achievable clock rate, area, and latency in clock cycles will be determined by the RTL description. However, not all paths should receive equal logic synthesis effort-multi-cycle paths represent an opportunity to spend logic synthesis effort elsewhere to achieve better design quality. In this paper, we perform multi-cycle optimisation on chained functional operations. We couple HLS and logic synthesis synergistically so multi-cycle paths can be identified and optimised coherently across both behavioral and logic levels. In addition, we perform multi-cycle path analysis at the behavioral level efficiently. We prove that our technique examines all reachable circuit state and finds multi-cycle paths including control flow and guarding conditions that improve the flexibility and power of the technique. Compared to LegUp, we achieve average 55% execution time improvement, 29% area improvement, and 68% time-area product improvement targeting FPGA architecture.

Behavioural transformation to improve circuit performance in high-level synthesis

2005

Early scheduling algorithms usually adjusted the clock cycle duration to the execution time of the slowest operation. This resulted in large slack times wasted in those cycles executing faster operations. To reduce the wasted times multi-cycle and chaining techniques have been employed. While these techniques have produced successful designs, its effectiveness is often limited due to the area increment that may derive from chaining, and the extra latencies that may derive from multicycling. In this paper we present an optimization method that solves the time-constrained scheduling problem by transforming behavioural specifications into new ones whose subsequent synthesis substantially improves circuit performance. Our proposal breaks up some of the specification operations, allowing their execution during several possibly unconsecutive cycles, and also the calculation of several data-dependent operation fragments in the same cycle. To do so, it takes into account the circuit latency and the execution time of every specification operation. The experimental results carried out show that circuits obtained from the optimized specification are on average 60% faster than those synthesized from the original specification, with only slight increments in the circuit area.

Loop Based Scheduling for High Level Synthesis

This paper describes a new loop based scheduling algorithm. The algorithm aims at reducing the runtime processing complexity of path based scheduling techniques. It partitions the control flow graph of the input specification into subgraphs before scheduling the different paths of each subgraph. Benchmark tests as well as simulation results on the scheduling algorithm indicate that the proposed algorithm results in sizeable reduction in runtime.

Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs

2007

In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced scheduling routine that uniformly distributes operations across states to reduce critical timing paths in the absence of accurate functional unit delay models. On average, results show improvements in frequency and run times for balanced scheduling over ASAP, ALAP, and force-directed scheduling. Additionally, we provide a methodology for precision-based delay modeling of operations. We present a balanced chaining routine that, given a target frequency, uses this modeling technique to reduce the number of clock cycles in the design. Results show approximately 20% improvement on average in run times when incorporating our balanced chaining routine with scheduling. Applying balanced chaining in a high-level synthesis tool allowed performance improvements between 8-29× for large, complex applications. Our method for modeling operation delays is shown to be accurate in estimating delays for operation chaining during high-level synthesis.

A PIPELINE SCHEDULING ALGORITHM FOR HIGH-LEVEL SYNTHESIS

In proc. of IFAC Workshop on Programmable Devices and Systems Conference PDS’03, Ostrava,, 2003

Scheduling is the most important task in high-level synthesis process, while pipelining is highly important for realising high-performance digital components. This paper presents a pipeline list-based scheduling algorithm, which performs forward and backward pipelining. The forward priority function is based on incorporating some information extracted from data flow graph (DFG) structure to guide the scheduler to find near-optimal/optimal schedules quickly. The algorithm has a flexible procedure cycle, which allows designers to make efficient area-performance trade-offs by using different strategies employed. Designers can choose between doing forward / backward pipelining with or without resource sharing combined with clock cycle selection, pipe stage delay determination. Experimental results with standard benchmarks show the effectiveness of the proposed algorithm.

Bridging the domains of high-level and logic synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002

High-level synthesis operates on internal models known as control/data flow graphs (CDFG) and produces a register-transfer-level (RTL) model of the hardware implementation for a given schedule. For high-level synthesis to be efficient, it has to estimate the effect that a given algorithmic decision (e.g., scheduling, allocation) will have on the final hardware implementation (after logic synthesis). The main problem in evaluating this effect is that the CDFGs are very distinct from the RTL/gate-level models used by logic synthesis. This makes it impossible to estimate hardware costs accurately. Moreover, the fact that high-level and logic synthesis operate on different internal models precludes on-the-fly interactions between these tools. This paper presents a solution to these problems consisting of a novel internal model for synthesis which spans the domains of high-level and logic synthesis. This model is an RTL/gate-level network capable of representing all possible schedules that a given behavior may assume. This representation allows high-level synthesis algorithms to be formulated as logic transformations and effectively interleaved with logic synthesis.

Timing variation-aware scheduling and resource binding in high-level synthesis

ACM Transactions on Design Automation of Electronic Systems, 2011

Due to technological scaling, process variations have increased significantly, resulting in large variations in the delay of the functional units. Hence, the worst-case approach is becoming increasingly pessimistic in meeting a certain performance yield. The problem therefore is to increase the performance as much as possible while maintaining the desired yield. In this work, we introduce an integer linear programming (ILP) formulation for scheduling and resource binding in high-level synthesis (HLS) which tries to mitigate the effect of timing variations. In the presence of delay variations of resources, as chained resources can give a better latency and performance yield trade-off, instead of considering them independently, we consider external chaining of resources, that is, two or more resources are connected by external wiring, and exploit operation chaining. Without violating the yield constraints, the proposed ILP formulation chains two consecutive operations and binds these ...

Scheduling Strategies in High-Level Synthesis

Informatica (slovenia) - INFORMATICASI, 1994

The paper describes objectives of high-level synthesis. It concentrates on operation schedulingstrategies and the interaction with the resource allocation. Some transformationaland iterative/constructive scheduling algorithms are described. Moreover, a new scheduling/allocation approach is presented and compared with other known algorithms. Finally,some open problems of the high-level synthesis are given.Keywords: High-level synthesis, scheduling, allocation.?This work has been...