Compact delay modeling of latch-based threshold logic gates (original) (raw)

Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic

Lecture Notes in Computer Science, 2004

The main result is the development, and delay comparison based on Logical Effort, of a number of high speed circuits for common arithmetic and related operations using threshold logic. The designs include 8 to 64-input AND, 4-bit carry generate, and the carry-out of a (7,3) parallel (population) counter. The circuits are designed using both domino gates and the recently proposed CMOS Charge Recycling Threshold Logic (CRTL). It is shown that compared to domino, the CRTL design examples are typically between 1.3 and 2.7 times faster over a wide range of load values, while presenting the same input capacitance to the driver.

Logical effort delay modeling of sense amplifier based charge recycling threshold logic gates

2003

In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in silicon, with improved performance and power dissipation compared to conventional logic. In this work, the problem of estimating the delay of circuits based on the Charge Recycling Threshold Logic (CRTL) gate implementation is addressed. A delay model is developed based on the recently proposed theory of Logical Effort. The model allows evaluation and comparison of high speed designs implemented in CRTL and conventional logic, The model is applied to the design of the 4-bit block carry-generate function and wide AND gates.

Delay analysis of CMOS gates using modified logical effort model

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005

In this paper, modified logical effort (MLE) technique is proposed to provide delay estimation for CMOS gates. The model accounts for the behavior of series-connected MOSFET structure (SCMS), the input transition time, and internodal charges. Also, the model takes into account deep submicron effects, such as mobility degradation and velocity saturation. This model exhibits good accuracy when compared with Spectre simulations based on BSIM3v3 model. Using UMC's 0.13-m and TSMC's 0.18-m technologies, the model has an average error of 4.5% and a maximum error of 15%.

Understanding the Effect of Process Variations on the Delay of Static and Domino Logic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000

In this paper, the effect of process variations on delay is analyzed in depth for both static and dynamic CMOS logic styles. Analysis allows for gaining an insight into the delay dependence on fan-in, fan-out, and sizing in sub-100-nm technologies. Simple but reasonably accurate models are derived to capture the basic dependences. The effect of process variations in transistor stacks is analytically modeled and analyzed in detail. The impact of both interdie and intradie variations is evaluated and discussed. Interestingly, the input capacitance of static and dynamic logic is shown to be rather insensitive to variations. The delay variability was also shown to be a weak function of the input rise/fall time and load. Analysis shows that domino logic circuits suffer from a doubled variability as compared to the static CMOS logic style. The positive feedback associated with the keeper transistor is shown to be responsible for the variability increase, which, in turn, limits the speed performance. This adds to the well-known speed degradation due to the current contention associated with the keeper transistor. Monte Carlo simulations on a 90-nm technology, including layout parasitics, are performed to validate the results.

Delay optimization of CMOS logic circuits using closed-form expressions

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040)

CMOS remains the mainstream IC technology and optimization of digital CMOS circuits is a major focus of research. This paper presents a comprehensive model for estimation and optimization of the delay in submicron digital CMOS circuits. Our delay model for a logic gate depends on the topology of the gate, the size and topology of the preceding gate, and the load. This model is explicit in terms of the widths of the transistors and lead to closed-form formulas for optimization of digital CMOS gates. These formulas are simplified and approximated into rules of thumb for quick optimization and obtaining initial guess for running a CAD tool. Delay optimization of a critical path is performed by solving a set of non-linear transistor sizing formulas using iteration. Very good agreement is observed between the model and HSPICE simulations.

A Compact Model of Threshold Switching Devices for Efficient Circuit Simulations

arXiv (Cornell University), 2023

In this paper, we present a new compact model of threshold switching devices which is suitable for efficient circuit-level simulations. First, a macro model, based on a compact transistor based circuit, was implemented in LTSPICE. Then, a descriptive model was extracted and implemented in MATLAB, which is based on the macro model. This macro model was extended to develop a physical model that describes the processes that occur during the threshold switching. The physical model derived consider a delay structure with few electrical components near to the second junction. The delay model incorporates an internal state variable, which is crucial to transform the descriptive model into a compact model and to parameterize it in terms of electrical parameters that represent the component's behavior. Finally, we applied our model by fitting i-v measured data of an OTS device manufactured by Western Digital Research.

Efficient timing analysis for CMOS circuits considering data dependent delays

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1998

Both long and short path delays are used to determine the valid clocking for various CMOS circuits such as single phase latching, asynchronous, and wave pipelining. Therefore, accurate estimation of both long and short path delays is very crucial in the designing and testing of high speed CMOS circuits. Most of the previous approaches in detecting long and short sensitizable paths assume that the rising and falling of gate delays are either xed or bounded. In fact the gate delay of CMOS circuits may also depend on how many and which inputs are rising or falling and the arrival times of those rising or falling inputs. For instance, the delay for a two-input CMOS NAND gate may vary as much as a factor of two based on whether one input or two inputs are changing. We shall refer a gate delay model which considers these factors as data dependent delay model. Gray, Liu and Cavin have proposed an approach based on simulation with event pruning to deal with this type of delay model 1]. In this paper, we propose several algorithms to compute the longest and shortest sensitizable path delays based on a data dependent delay model. A proposed algorithm which based on a combination of modi ed static (topological) timing analysis and path sensitization techniques seems to o er the best performance. The results obtained have shown to be more accurate than the traditional path sensitization approach based on bounded delay model. Y=max(t1+dmax(A"B), t2+dmax(AB"), min(min(t1,t2)+ , max(t1, t2))+dmax(A"B")) Under the assumption that t1 and t2 are correct rising times, this means that Y1 t1, Y2 t2. We need to prove XX Y. Since the real rising time of c may come from the following cases, 1. A"B, the rising time is x + delay(A"B) (x 2 X1, Y1]) t1 + dmax(A"B). 2. AB", the rising time is y + delay(AB")) (y 2 X2, Y2]) t2 + dmax(AB"). 3. A"B", the rising time is z+delay(A"B"), z 2 max(x1, x2), min(min(Y1, Y2)+ , max(Y1, Y2))]. Y1 and Y2 are smaller than or equal to t1 and t2 respectively, so z is not bigger than min(min(t1,t2)+ , max(t1, t2)), so z+ delay(A"B") min(min(t 1 , t 2 )+ , max(t 1 , t 2 ))+dmax(A"B"). XX Y is proved. For the falling time of G, we can prove this similarly. 2 Even though the transition delay do not satisfy monotone speedup property 4], the result obtained by the above algorithm does satisfy this property. Lemma 1 The result obtained by the algorithm for long transition delay satis es monotone speedup property. Proof This can be proved similarly to the proof of Theorem 1. We shall not present here. 2 Now we will discuss how to estimate the shortest transition path delay. Suppose that gate G has two inputs a, b and one output c and e ar , e af , e br , e bf , e cr and e cf denote the earliest possible rising and falling times of lead a, b and c respectively, then we have the following formulas for the data dependent delay model and bounded delay model. 1 G is an AND gate, under data dependent delay model e cr = min(e ar + dmin(a"b), e br + dmin(ab"), max(e ar , e br ) + dmin(a"b")) e cf = min(e af + dmin(a#b), e bf + dmin(ab#), max(max(e af , e bf )-, min(e af , e bf ))+dmin(a#b#)) under bounded delay model 10 e cr = min(t ar , t br ) + min(dmin(a"b"), dmin(ab"), dmin(a"b")) e cf = min(e af + dmin(a#b), e bf + dmin(ab#), max(max(e af , e bf )-, min(e af , e bf ))+dmin(a#b#)) 2 G is an OR gate, under data dependent delay model e cr = min(e ar +dmin(a" b), e br +dmin(ab "), max(max(e ar , e br )-, min(e ar , e br ))+dmin(a"b")) e cf = min(e af +dmin(a# b), e bf +dmin(ab#), max(e af , e bf ) + dmin(a#b#)) under bounded delay model e cr = min(e ar +dmin(a"b), e br +dmin(ab"), max(e ar , e br )+dmin(a"b")) e cf = min(e af +dmin(a#b), e bf +dmin(ab#), max(e af , e bf )+dmin(a#b#)) 3 G is a NAND gate, under data dependent delay model e cf = min(e ar +dmin(a"b), e br +dmin(ab"), max(e ar , e br )+ dmin(a"b")) e cr = min(e af +dmin(a#b), e bf +dmin(ab#), max(max(e af , e bf )-, min(e af ,e bf ))+dmin(a#b#)) under bounded delay model e cf = min(t ar , t br )+min(dmin(a"b"), dmin(ab"), dmin(a"b")) e cr = min(t af , t bf )+min(dmin(a#b), dmin(ab#), dmin(a#b#)) 4 G is a NOR gate, under data dependent delay model e cf =min(e ar +delay(a" b), e br +dmin(ab "), max(max(e ar , e br )-, min(e ar , e br ))+dmin(a"b")) e cr = min(e af +dmin(a# b), e bf +dmin(ab#), max(e af , e bf ) + dmin(a#b#)) under bounded delay model e cf = min(e ar +dmin(a"b), e br +dmin(ab"), max(e ar , e br )+dmin(a"b")) e cr = min(e af +dmin(a#b), e bf +dmin(ab#), max(e af , e bf )+dmin(a#b#)) If G is an inverter gate with input a and output c, the formulas for both the data dependent delay model and bounded delay model are: e cr = e af + dmin(a#), e cf = e ar + dmin(a") We can get similar formulas for a gate with more than 2 input leads.

DESIGN OF AN ENERGY-EFFICIENT CONSTANT DELAY LOGIC FOR LOW POWER APPLICATIONS

An Energy Efficient Constant Delay Logic (EE-CDL) is proposed in this thesis to reduce the power consumption for low power applications. The EE-CDL is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. It has a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage are ready. The proposed logic style requires low power when compared to the existing CDL. The proposed circuit is designed and using 90-nm, CMOS technology file with supply voltage 1.2V. An inverter is designed using energy efficient feedthrough logic and simulated in MicroWind. The simulation result shows that the proposed logic reduces the power consumption by 88%, 83% and 56% when compared with FTL, Low Power FTL (LP-FTL) and Constant Delay Logic (CDL) respectively. The problem of requirement of inverter as in dynamic logic is completely eliminated in the proposed logic.

Modeling and Implementation of Threshold Logic Circuits and Architectures

2010

for their friendship and collaborative input, and extend a very special thanks to Dr. Kryzsztof Berezowski, who provided invaluable support and insight without which this work would not be possible. Additionally, I would like to extend my thanks to Dr. David Blaauw at the University of Michigan and his students, particularly Carlos Tokunaga and Zhiyoong Foo, for their assistance with the CAD flow used in the fabrication of the multiplier test chip. I would also like to express my deepest thanks for the funding received from the National Science Foundation under award CCF-070283, the Science Foundation Arizona SFAZ-SBC and the Stardust Foundation, the Consortium for Embedded Systems, and the Department of Computer Science and Engineering through principal investigator Dr. Sarma Vrudhula, which provided my salary as a full time research assistant, tuition, travel expenses, and additional benefits from 2005 to 2010. Finally, I would also like to thank my family for their love and support throughout this long and arduous process.

High Speed and Low Power ASIC Using Threshold Logic

Authors : Navaneetha Velammal M1, Sharanabasaveshwar G. Hiremath2, R.Prem Ananth3, Rama S4 Abstract:-In this paper, a new circuit architecture of a differential threshold logic gate called PNAND is proposed. The main purpose of this work to reduce the leakage, power and area of standard ASIC Circuits. By predicting the performance comparison of some electrical quantity such as charge, voltage or current, the implementation of threshold logic gates (TLG) is considered in this paper. Next a hybridization technique is done by replacing the flipflops and parts of their clocks with PNAND cells is Proposed. At last the proposed PNAND cell is hybridized with conventional logic cells, which will result in lower power consumption, leakage and area. This paper is proposed using Cadence® Virtuoso Schematic Editor at 180nm technology. Several design circuit methodologies such as retiming and asynchronous circuit design can used by the proposed threshold logic gate effectively.