Low Power Signal Processing with Translinear Networks (original) (raw)
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A promising new approach to shorten the design trajectory of analog integrated circuits without giving up functionality is formed by the class of dynamic translinear circuits. This paper presents a structured design method for this young, yet rapidly developing, circuit paradigm. As a design example, a 1-V 1.6-A class-AB translinear sinh integrator for audio lter applications, is presented.
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This paper reports a general methodology and a computer-aided design (CAD) tool (BECAS 1.0) for synthesis of linear analog functions with a network of operational transconductance amplifiers (OTAs). Efficient analog circuits have been synthesized with the CAD tool and reported along with the simulation results. SPICE simulated results of the synthesized circuit match closely with those derived theoretically from the input transfer function. A first-order low-pass filter employing a minimum number of OTAs is used in the design as the basic building block. The number of OTAs employed to realize an analog function can be minimized in the optimization phase of the synthesis algorithm.
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This Chapter is devoted to review the static and dynamic translinear paradigm in the last years (2000)(2001)(2002)(2003)(2004)(2005)(2006)(2007)(2008)(2009)(2010)(2011). Many papers have been written since then extending the application fields, proposing novel and new analog circuits and systems based on this principle, where MOS transistors are working in new regions of operation. These ongoing researches on translinear circuits arised of the requirements of low-power and low-voltage, which are forcing the technology at its maximum performance, and this paradigm can be an excellent solution. The Chapter is presented as a summary of the advances in this field from different perspectives such as applications, circuits, and regions of operation of transistors, emphasizing the advantages and drawbacks. Also, some unsolved general trends are mentioned and research lines are described with the aim of identifying the main frame for this paradigm.
A current driven, programmable gain differential pair using MOS translinear circuits
1998
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Translinear Signal Processing Circuits in Standard CMOS FPAA
—In this paper, the implementation of signal processing circuits on a novel translinear Field-Programmable Analog Array (FPAA) testchip is reported. The FPAA testchip is based on a 0.35-micron, fully CMOS translinear element, which is the core block of a reconfigurable analog cell. The FPAA embeds a 5 × × × 5 cell array. As implementation examples, a four-quadrant multiplier with five decade dynamic range and a programmable fourth-order low-pass filter with up to 7 M Hz bandwidth have been mapped on the translinear FPAA. 14 cells have been used for the four-quadrant multiplier while 18 cells were needed for the fourth-order low-pass filter.
This paper presents a C++ code program used to synthesize the trans-linear networks using rational approximation that are followed by continuous and partial fractions decomposition. Both the partial fractions decomposition algorithm and continued fractions decomposition algorithm used for development of this program are new, different by comparison with those incorporated in TLSS program (translinear circuits synthesis program developed by authors in period 1999-2000). In this paper will be presented only continued fractions decomposition. Comparative to the initially TLSS algorithm variant this continued fractions decomposition algorithm resolve same cases that are not considered in previous variant and it is more faster.