Investigation of a nanoscale grooved stepped gate MOSFET to explore the self-heating effect (original) (raw)

2019 Devices for Integrated Circuit (DevIC), 2019

Abstract

This work reports a new grooved gate silicon-on-insulator (GG-SOI) MOSFET with multi-layered (SiO2/Si3N4/SiO2) buried insulator structure to reduce self-heating effect (SHE). The proposed model is simulated using the Sentaurus TCAD simulator. As the thermal conductivity of SiO2/Si3N4/SiO2 buried insulator is higher than SiO2 buried layer, this innovative grooved gate SOI model is able to reduce the self-heating effect of the conventional GG-SOI MOSFET. Thus appropriate for high temperature solicitations. Performance comparison has been done between the multi-layer-buried recessed channel SOI and conventional SiO2 based GG-SOI MOSFET. The presented structure has well controlled the device temperature against the low thermal conductivity of conventional GG-SOI MOSFET. Further step gate concept is used for the improvement of analog performance and short channel effects (SCEs). Simulation results reveal the enhanced performance manifested by the proposed structure in terms of increased drain current, reduced device temperature and increased electron mobility.

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