Characterisation and Evaluation of the Underfill Encapsulants for Flip Chip Assembly (original) (raw)
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Recent Advances in Flip-Chip Underfill: Materials, Process, and Reliability
—In order to enhance the reliability of a flip-chip on organic board package, underfill is usually used to redistribute the thermomechanical stress created by the coefficient of thermal expansion (CTE) mismatch between the silicon chip and organic sub-strate. However, the conventional underfill relies on the capillary flow of the underfill resin and has many disadvantages. In order to overcome these disadvantages, many variations have been invented to improve the flip-chip underfill process. This paper reviews the recent advances in the material design, process development, and reliability issues of flip-chip underfill, especially in no-flow under-fill, molded underfill, and wafer-level underfill. The relationship between the materials, process, and reliability in these packages is discussed.
IEEE Transactions on Electronics Packaging Manufacturing, 2002
Solder bumped Flip Chips on low cost substrates with three different epoxy-based no-clean flux liquid-like no-flow underfills are presented in this study. This paper includes evaluation of three commercial no-flow underfills and characterization of material and process parameters. Important materials and process parameters, such as curing temperature and time, thermal coefficient of expansion, storage modulus, loss modulus, tand, glass transition temperature, moisture uptake, solder reflow, and post curing are discussed in this work. Curing mechanism during reflow of no-flow underfills will be illustrated in this paper and a comparison of noflow underfill and conventional underfill will be also addressed. Also, cross-sections are examined for a better understanding of the effects of these no-flow underfill materials on the interconnects of the Flip Chip assemblies. Shear and thermal-cycling tests and results of these Flip Chip assemblies are reported and analyzed.
ECTC 2011, 2011
We developed a latent curing, low outgassing wafer level underfill (WLUF) material and applied fast temperature ramping to achieve 100% electrically and metallurgically good flip chip solder joints. Also, void formation within the underfill material during the bonding process was minimized. Subsequently, these voids were virtually eliminated during a post cure process of the WLUF material which uses pulsed amplitude pressure. A WLUF with 60% (weight) filler was applied by spin coating onto a wafer with Pb-free solder bumps. Following B-stage curing at 90 o C, the thickness was measured to be 20 microns over the solder bump height. In the B-staged state, this WLUF is stable at room temperature for several weeks. After the wafer was diced into chips, a chip was aligned and joined to a substrate with an optimized heating and cooling cycle. This WLUF assembly process has been evaluated using a flip chip test vehicle with 150 micron pitch and 3,300 area array solder bumps. The chip bumps were SnAg solder and the pre-solder on the substrate was SnAgCu. The size of the test chip was 9 x 13 mm and the test substrate was 42.5 x 42.5 mm. The test chip and substrate were designed to allow both two and four wire contact resistance measurements of the electrical interconnect structures. We successfully demonstrated 100% electrically and metallurgically good Pb-free joints. Voids inside the WLUF after flip chip bonding were decreased significantly using the pulsed amplitude pressure, post cure process. Scanning acoustic microscopy (SAM) analysis showed nearly void-free underfill bonding. After JEDEC level three preconditioning, environmental stress testing was completed and included 1000 deep thermal cycles of-55 to 125 o C; 1000 hrs at 85C/85% temperature and humidity; and 1000 hrs of 150 o C high temperature storage. Contact resistance measurements were made at time zero, after preconditioning and every 250 cycles or hours of environmental stress. The contact resistance measurements were stable on all parts. Detailed material and process development, and reliability test results are described in this paper.
Development of wafer level underfill material and process
Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003), 2003
The flip-chip on organic substrate has relied on underfill to enhance the solder joint reliability. The invention of the wafer level underfill technology has greatly improved the production efficiency of flip-chip process. The development of wafer level underfill material and process relies on the fundamental understanding of the underfill curing process. A wafer level underfill material is developed; its curing kinetics is modeled using autocatalytic model, based on which the B-stage feasibility of the underfill is investigated. The B-stage properties of the underfill are characterized in terms of its Tg, hardness, adhesion, dicing and storage capability. The developed wafer level underfill displays high curing latency required in the reflow process, as well as good mechanical properties after B-stage. The underfill is applied on a 6 inch bumped wafer and B-staged. Then the wafer is diced into individual components and assembled onto the FR-4 board.
No-flow underfill flip chip assembly––an experimental and modeling analysis
Microelectronics Reliability, 2002
In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfill: the application and curing of the former can be undertaken before and during the reflow process. This advantage can be exploited to increase the flip-chip manufacturing throughput. However, adopting a no-flow underfill process may introduce reliability issues such as underfill entrapment, delamination at interfaces between underfill and other materials, and lower solder joint fatigue life. This paper presents an analysis on the assembly and the reliability of flip-chips with no-flow underfill. The methodology adopted in the work is a combination of experimental and computer-modeling methods. Two types of no-flow underfill materials have been used for the flip chips. The samples have been inspected with X-ray and scanning acoustic microscope inspection systems to find voids and other defects. Eleven samples for each type of underfill material have been subjected to thermal shock test and the number of cycles to failure for these flip chips have been found. In the computer modeling part of the work, a comprehensive parametric study has provided details on the relationship between the material properties and reliability, and on how underfill entrapment may affect the thermal-mechanical fatigue life of flip chips with no-flow underfill.
Effect of Underfill Entrapment on the Reliability of Flip-Chip Solder Joint
Journal of Electronic Packaging, 2004
The application of underfill materials to fill up the room between the chip and substrate is known to substantially improve the thermal fatigue life of flip chip solder joints. Nowadays, no-flow underfill materials are gaining much interest over traditional underfill as the application and curing of this type of underfill can be undertaken before and during the reflow process and thus aiding high volume throughput. However, there is always a potential chance of entrapping no-flow underfill in the solder joints. This work, attempts to find out the extent of underfill entrapment in the solder joints and its reliability effect on the flip chip packages. Some unavoidable underfill entrapments at the edges of the joint between solder bumps and substrate pads are found for certain solder joints whatever bonding conditions are applied. It is interesting to report for the first time that partial underfill entrapment at the edges of the solder joint seems to have no adverse effect on the fat...
Void Formation Study of Flip Chip in Package Using No-Flow Underfill
IEEE Transactions on Electronics Packaging Manufacturing, 2000
The advanced flip chip in package (FCIP) process using no-flow underfill material for high I/O density and fine-pitch interconnect applications presents challenges for an assembly process that must achieve high electrical interconnect yield and high reliability performance. With respect to high reliability, the voids formed in the underfill between solder bumps or inside the solder bumps during the no-flow underfill assembly process of FCIP devices have been typically considered one of the critical concerns affecting assembly yield and reliability performance. In this paper, the plausible causes of underfill void formation in FCIP using no-flow underfill were investigated through systematic experimentation with different types of test vehicles. For instance, the effects of process conditions, material properties, and chemical reaction between the solder bumps and no-flow underfill materials on the void formation behaviors were investigated in advanced FCIP assemblies. In this investigation, the chemical reaction between solder and underfill during the solder wetting and underfill cure process has been found to be one of the most significant factors for void formation in high I/O and fine-pitch FCIP assembly using no-flow underfill materials.
The International Journal of Advanced Manufacturing Technology, 2019
Underfill encapsulation process regularly encounters productivity issue of long filling time that incurs additional manufacturing costs. The package was optimized to attain least filling time while retaining the miniature package size. This paper presents a new analytical generalized filling time chart that was generated using the latest regional segregation-based analytical filling time model. The governing model was well-validated to the industrial underfill benchmark data with discrepancy of less than 10.42%. The filling time chart gives non-dimensionalized filling times at various combinations of bump pitch, gap height, and contact angle. Subsequently, another chart that gives the filling time coefficient was derived from the filling time chart to compute the instantaneous filling time directly. Interestingly, two variation trends of bump pitch were observed from the filling time chart that were distinguishable based on the critical contact angle. When the contact angle exceeds its critical value, there exists the critical bump pitch that restricted the miniature design of the package. On contrary, all past literatures only elucidated one variation trend of bump pitch without introduced the critical contact angle. Overall, the analytical filling time chart benefited the optimization study as it concisely composed all parametric variation trends of filling time as well as the criticality of underfill parameters. Thus, time and effort can be greatly reduced upon compared with the conventional numerical-based optimization work, without compromising the accuracy aspect.
Wafer Level Underfill Processing
Packaging of Electronic and Photonic Devices, 2000
Underfill materials play a major role in the reliability of flip chip packages. These adhesives have been the subject of much research and development in the last few years, and much improvement in material performance has been obtained. However, the assembly method still remains unchanged, with the underfill being dispensed at the individual die level after flip chip reflow. Even with the arrival of “no-flow” underfills, assembly still requires depositing the underfill material onto the flip chip site prior to positioning the flip chip die. Processing underfill at the wafer level brings in a new paradigm shift to the area of flip chip packaging. Precoating the wafer with the underfill will create significant savings in both time and money. The application cycle time of the wafer level process becomes equivalent to a single dispensing operation for all the good dies on the wafer. This paper will present results obtained with screen printing used as the application method for the waf...