Renovated 32 Bit ALU Using Hybrid Techniques (original) (raw)
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Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors
2002
Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique technique for arithmetic computations based on 16 Sutras (Formulae). Transistor level implementation (ASIC) of Vedic Mathematics based 32-bit multiplier for high speed low power processor is reported in this paper. Simple Boolean logic is combined with 'Vedic' formulas, which reduces the partial products and sums generated in one step, reduces the carry propagation from LSB to MSB. The implementation methodology ensure substantial reduction of propagation delay in comparison with Wallace Tree (WTM), modified Booth Algorithm (MBA), Baugh Wooley (BWM) and Row Bypassing and Parallel Architecture (RBPA) based implementation which are most commonly used architectures. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using standard 90nm CMOS technology. The propagation delay of the resulting 32×32 multiplier was only ~1.06 us and consumes ~132 uW power. The implementation offered significant improvement in terms of delay and power from earlier reported ones.
Design of 32 Bit Vedic Multiplier using Carry Look Ahead Adder
The digital architecture is mainly used in all type of real world application architectures and thus the architecture modify based on enhancement purpose. The VISI is to optimize the any type of digital architecture. Multiplication is an important fundamental function in arithmetic logic operation. Computational performance of a DSP system is limited by its multiplication performance and since, multiplication dominates the execution time of most DSP algorithms. Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time than addition and subtraction. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculation based on 16 Sutras. Our work is to develop the 32 –bit Vedic multiplier architecture using carry look ahead adder technique.
High Performance ALU Using Carry Look-ahead Adder
CVR Journal of Science & Technology, 2018
A Low Power 8-bit Arithmetic Logic unit (ALU) using a Carry look-ahead adder (CLA) and placing Low Vt (LVt) cells in Critical path is anticipated. The ALU is designed in 90nm CMOS technology. ALU is the most essential circuit in any processor. It consists of AE, LE, CLA and CE. This ALU is designed to calculate Arithmetic and Logical operations. Power and Delay values of different 8-bit adders like CLA, Sparse and Ripple Carry Adder (RCA) are designed and compared. The simulation results show that the design of ALU using CLA and incorporating High Vt and Low Vt cells in the CLA gives more power and delay efficient than with only Standard threshold voltage cells.
64bit Hybrid Adder for ALU Design Applications
International Journal of Innovative Technology and Exploring Engineering (IJITEE), 2020
The Arithmetic Logic Unit is an important component of any Central Processing Unit. An improvement of the speed, area, and power consumption of an ALU directly promotes the performance of the system. Thus, optimization of the ALU design is necessary and for this reason several common adders such as the ripple carry adder, etc. and a proposed model of a 64bit hybrid adder were designed, and a comparative analysis of their performance was studied. The proposed hybrid adder was developed using an 8bit Ripple Carry adder that evaluates the LSB followed by a Carry skip adder block consisting of a 4bit Carry Skip Adder, an 8bit Carry Skip, another 8bit Carry Skip, followed by a 4bit Carry Skip Adder, and finally the MSB is calculated by a 32bit Carry Select Adder. The adders were designed in Verilog on ModelSim-Altera 10.1d (Quartus II 13.0sp1) and later the schematic was obtained on Genus Synthesis (RTL Compiler) of Cadence for ASIC design using 45nm technology. Each adder showed some advantages, but the proposed hybrid adder optimized all aspects of the model while increasing the speed of the device.
IJERT-An Efficient Method to Implement Optimized Adder in ALU
International Journal of Engineering Research and Technology (IJERT), 2014
https://www.ijert.org/an-efficient-method-to-implement-optimized-adder-in-alu https://www.ijert.org/research/an-efficient-method-to-implement-optimized-adder-in-alu-IJERTV3IS100661.pdf Carry select Adder (CSLA) is known to be the fastest adder among the other adder structures. This work uses an area efficient carry select adder by reducing redundant operations. The proposed CSLA method has been developed efficient gate level modification to significantly reduce the area, Power and delay. In the existing adder system, the multiplexer is used to select the exact output according to the logic states of carry-in signal. In the proposed work, the redundant operations are reduced by optimizing the selection unit and this proposed adder is implemented in Arithmetic and Logic Unit(ALU). The result analysis shows that the proposed architecture achieves the three folded advantages in terms of area, power and delay.
International Journal of Scientific Research in Science and Technology, 2022
16-bit RISC processor with Vedic multiplier architecture is used in this project. In addition to multiplier which is implemented using vedic mathematics we are also proposing an adder which is hybrid adder for building higher bit adders in an area efficient which is implemented in addition as well as for compression in vedic mathematic to obtain the output. The multiplier unit is developed utilizing Vedic Sutras, which is the primary accomplishment of this study. The primary premise of Vedic mathematics is to minimize the computational complexity by reducing the usual calculation of conventional mathematics to a very simple calculation. The suggested RISC processor is extremely primitive, and it can only execute 14 instructions. The accomplishment of this study is that in the case of MAC and ALU, power savings and minimized latency are realized as compared to traditional ALU and MAC. Following that, the Vedic MAC and ALU are combined with other processing blocks to create a 16-bit Vedic processor. As a result, the major features of the developed RISC processor are an increase in operating speed, a decrease in power consumption, and a reduction in area consumption.
Design and Implementation of Novel 4-Bit Alu
Lecture Notes in Electrical Engineering, 2020
The paper's main concern is to reduce the power of the adder and multiplier modules, which are significant ALU functional units, thus reducing the overall power utilization without compromising the processor's speed. The ALU circuit ensures that arithmetic or logical operation is carried out only at the same time so that only one set of circuits is active at the same time. Adders constitute a necessary part of every modern integrated circuit. The requirement of an adder is that in terms of power consumption and chip size, it is primarily fast and secondary efficient. The adder topology used in this work is the ripple carrying adder, the look-ahead adder, the adder carrying skip, the adder carrying selection, the adder carrying increase, the adder carrying save and the adder carrying bypass. The Verilog compares module functionality and presentation problems such as area, power dissipation and propagation delay. Every processor's performance depends on its power and delay. To get an effective processor, the power and delay should be lower. The most commonly used architecture in processors is multiplier. If the multiplier power and delay are reduced, then the efficient processor can be generated.
Design and Analysis of Different Type Single Bit Adder for ALU Application
In these dissertation four types of 1-bit adder has been designed and simulated using 180nm CMOS technology in tanner tool at a various supply voltage from1.0V to 1.8 V & compare their results with respect to various parameters like delay, area & power consumption. The adder is the most commonly used arithmetic block of the Central Processing Unit (CPU) and Digital Signal Processing (DSP), therefore its performance and power optimization is of utmost importance. With the technology scaling to deep sub-micron, the speed of the circuit increases rapidly. Due to continuous scaling of the transistor size and reduction of the operating voltage has led to a significant performance improvement of integrated circuits. Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. At the same time, the power consumption per chip also increases significantly due to the increasing density of the chip. Therefore comparison has been carried out by assuming the circuits with minimum size transistors, to minimize the power consumption. Power consumption is a function of load capacitance, frequency of operation, and supply voltage. A reduction of any one of these parameter is beneficial. A reduction in power consumption provides several benefits. Less heat is generated, which reduces problems associated with high temperature, such as the need for heat sinks. This provides the consumer with a product that costs less.
Area Efficient Vedic Multiplier Based on Homogenous Hybrid Adder for RISC V Applications
International Journal of Scientific Research in Science and Technology, 2022
16-bit RISC processor with Vedic multiplier architecture is used in this project. In addition to multiplier which is implemented using vedic mathematics we are also proposing an adder which is hybrid adder for building higher bit adders in an area efficient which is implemented in addition as well as for compression in vedic mathematic to obtain the output. The multiplier unit is developed utilizing Vedic Sutras, which is the primary accomplishment of this study. The primary premise of Vedic mathematics is to minimize the computational complexity by reducing the usual calculation of conventional mathematics to a very simple calculation. The suggested RISC processor is extremely primitive, and it can only execute 14 instructions. The accomplishment of this study is that in the case of MAC and ALU, power savings and minimized latency are realized as compared to traditional ALU and MAC. Following that, the Vedic MAC and ALU are combined with other processing blocks to create a 16-bit Vedic processor. As a result, the major features of the developed RISC processor are an increase in operating speed, a decrease in power consumption, and a reduction in area consumption.
IJERT, 2014
This paper describes the implementation of a 32x32-bit multiply accumulate (MAC) unit designed using ancient Vedic mathematical techniques. This research work presents the efficiency of Urdhva Triyagbhyam Vedic method for multiplication which strikes a difference in actual process of multiplication itself. It enables the parallel generation of partial products and eliminates unwanted multiplication and addition steps. Multiply Accumulate unit is a key component in the most of the digital signal processors, in order to make a balance in the key performance characters such as speed, power and area, a gate level implementation of the design is adopted in the entire research work. An analysis of the best adder among some commonly available adders is carried out and the best adder is used for adding the partial product generated in the Vedic multiplication technique to reduce the combinational delay in the critical path. The proposed research work is coded in VHDL, and analysis in-terms of speed power and area is done on vertex 6 FPGA using Xilinx ISE 13.1 tool.