A Noise-Shaping Algorithm of Multi-bit DAC Nonlinearities (original) (raw)
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A Multibit Complex Bandpass AZAD Modulator with I, Q Dynamic Matching and DWA Algorithm
2006 IEEE Asian Solid-State Circuits Conference, 2006
A second-order multi-bit switched-capacitor complex bandpass ∆ΣAD modulator has been designed and fabricated for application to low-IF receivers in wireless communication systems such as Bluetooth and WLAN. We propose a new structure of a complex bandpass filter in forward path with I, Q dynamic matching which is equivalent to the conventional one but it can be divided into two separate parts. As a result, the ∆Σ modulator which constituted with our proposed complex filter can be completely divided into two separate parts too, and there are not any signal line crossing between the upper and lower paths by a complex filter and feedback from DACs. Therefore, the layout design of the modulator can be greatly simplified. Nine-level two quantizers and four DACs are used in the modulator for lower power implementation and higher SNDR, but the nonlinearities of DACs are not noise-shaped and the SNDR of the ∆Σ ADC degrades. We have employed a new complex bandpass Data-Weighted Averaging (DWA) algorithm to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy; it can be realized just by adding simple digital circuitry. Implemented in a 0.18-µm CMOS process and at 2.8V supply, the modulator achieves a measured peak signalto-noise-and-distortion (SNDR) of 64.5dB at 20MS/s with a signal bandwidth of 78kHz while dissipating 28.4mW and occupying a chip area of 1.82mm 2 .
International Journal of Advances in Applied Sciences (IJAAS), 2021
In general, the noise shaping responses, a cyclic second order response is delivered by the method of data weighted averaging (DWA) in which the output of the digital-to-analog convertor (DAC) is restricted to one of two states. DWA works efficiently for rather low levels of quantizing; it begins presenting considerable difficulties when internal levels of quantizing are extended further. Though, each added bit of internal quantizing causes an exponentially increasing in power dissipation, complexity and size of the DWA logic and the DAC. This gives a controlled seconnd order response accounting for the mismatch of the elements of DAC. The multi-bit DAC is made up of numerous single-bit DACs having values thereof chosen via a digital encoder. This research presents a discussion of the influence of mismatching between unit elements of the Delta-Sigma DAC. This results in a constrained second order response accounting for mismatch of DAC elements. The results of the simulation showed how the effectiveness of DWA method is in reducing band tones. Furthermore, DWA method has proved its efficiency in solving the mismatching of DAC unit elements. The noise of the mismatching elements is enhanced 11 dB at 0.01 with the proposed DWA, thereby enhancing the efficiency of the DAC in comparison to the efficiency of the DAC with no use of the circuit of DWA.
Complex-signal sigma-delta modulators for quadrature bandpass A/D conversion
Microelectronics Journal, 1996
This paper presents a study on complex-signal sigma-delta (ΣΔ) modulators suitable for quadrature bandpass analogue-to-digital conversion of signals in monolithic radio receivers. The noise-shaping in complex-signal modulators is not symmetric with respect to dc, i.e. the zeros in the noise transfer function are not complex-conjugate as in conventional bandpass modulators. First-order (L = 1), second-order (L = 2) and high-order (L > 2) cascade topologies are discussed together with design methodologies suitable for switched-capacitor (SC) realization. Complex-signal fully-differential SC integrators and sigma-delta modulators are also addressed. The concepts, design methodologies and circuits proposed have been validated through simulations made with TOSCA (V. Literali et al., IEEE Trans. CAD Integrated CAS, 12(9) (1993) 1376–1386) and SWITCAP-2 (K. Suyams et al., IEEE J. Solid-State Circuits, 25(6) (1990) 1403–1413).
Noise-Coupled Image Rejection Architecture of Complex Bandpass ΔΣAD Modulator
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2010
This paper proposes a new realization technique of image rejection function by noise-coupling architecture, which is used for a complex bandpass ΔΣAD modulator. The complex bandpass ΔΣAD modulator processes just input I and Q signals, not image signals, and the AD conversion can be realized with low power dissipation. It realizes an asymmetric noise-shaped spectra, which is desirable for such low-IF receiver applications. However, the performance of the complex bandpass ΔΣAD modulator suffers from the mismatch between internal analog I and Q paths. I/Q path mismatch causes an image signal, and the quantization noise of the mirror image band aliases into the desired signal band, which degrades the SQNDR (Signal to Quantization Noise and Distortion Ratio) of the modulator. In our proposed modulator architecture, an extra notch for image rejection is realized by noise-coupled topology. We just add some passive capacitors and switches to the modulator; the additional integrator circuit composed of an operational amplifier in the conventional image rejection realization is not necessary. Therefore, the performance of the complex modulator can be effectively raised without additional power dissipation. We have performed simulation with MATLAB to confirm the validity of the proposed architecture. The simulation results show that the proposed architecture can achieve the realization of image-rejection effectively, and improve the SQNDR of the complex bandpass ΔΣAD modulator.
Compensation of Nonlinearities in ΣΔ Modulators Using Digital Assisted Analog Electronics Approach
International Journal of Signal Processing Systems, 2014
This paper presents a Digital Signal Processing (DSP) technique to compensate nonlinearities in reconfigurable Sigma Delta (ΣΔ) Modulator. In order to design digitally enhanced transceiver, a problem of nonlinearities in these modulators should be addressed. The problem arises due to the constituent building block of ΣΔ Modulators i.e. Digital to Analog Converter (DAC). Since DAC is outside the ΣΔ signal path; the nonlinearities are not reduced by over-sampled quantization and shaping. In this paper, the nonlinearity effects of ΣΔ Modulator are captured by simulating the Signal to Noise Ratio (SNR), Signal to Noise and Distortion Ratio (SNDR), and Spurious Free Dynamic Range (SFDR). For correction, the nonlinearity affected samples are passed to a transversal filter where sample-by-sample compensation is done using the simulated ideal response as a reference. The Normalized Least Mean Square (NLMS) algorithm is employed to adjust and update the filter tap-weights. Simulation results show that for a three-tone input to 4-bit first order ΣΔ Modulator, the SNDR and SFDR improves by 24.6 dB and 34 dB respectively.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017
A 4-bit, third-order, continuous-time modulator is presented for use in wireless communications systems. Based on small-signal noise models, analyses for reducing noise in the feedback digital-to-analog converter (DAC) are presented in detail. This enables easy performance/area optimization for the DAC unit elements and the RC noise filter in the DAC bias circuits. To obtain high linearity while simplifying the DAC design, circuit-and layout-level design techniques for minimizing switching time mismatches among and inside the DAC unit elements are presented. As a result, glitch-induced harmonic distortion is greatly reduced, requiring only a simple dataweighted averaging for the multibit DAC. In combination with multipath multistage op amps used to implement active-RC integrators, the presented techniques make it feasible to design a high-performance modulator with low power and small area, which is desired in many wireless communications systems. The experimental prototype, implemented in a 28-nm CMOS technology, achieves a 72.6-dB dynamic range, a 70.7-dB peak SNR, and a 70.1-dB peak signal-to-noise plus distortion ratio for a signal bandwidth of 20 MHz. The total power consumption is 6 mW from a 1-and 1.4-V supply, of which analog and digital circuits dissipate 4.5 and 1.5 mW, respectively. The total active area is 0.058 mm 2 .
Low-distortion bandpass - modulator for wireless radio receivers
Electronics Letters, 2005
A low-distortion bandpass sigma-delta modulator is proposed. It was found that the key to improving linearity is to add a feedforward signal path in a double-delay resonator bandpass structure. The proposed technique improves the tonal behaviour even at low oversampling ratio and can be applied for any order of modulator. Based on the proposed architecture, a fourth-order single-bit sigma-delta modulator can achieve a dynamic range of 84 dB and a spurious free dynamic range of 98 dB at 10.71 MHz with a signal bandwidth of 200 kHz, making it ideal for a narrowband IF-sampled wireless receiver designed for compliance with GSM=GPRS standards.
Spectral shaping of DAC nonlinearity errors through modulation of expected errors
2001
Traditionally, delta-sigma modulation has been used for shaping of quantization noise. We present a modified version of delta-sigma modulation which also takes into account unwanted nonlinearities by feeding back not only the quantization error, but also the expected physical error. Behavioral-level simulations of a 5th-order structure showing an improvement of up to 4 effective bits are included
Reconfigurable complex digital Delta-Sigma modulator synthesis for digital wireless transmitters
2008
Digital generation of radio-frequency signals is a key concept of software defined radio. One of the main difficulties for multi-standard transmitter design based on delta-sigma (DeltaSigma) modulators is to respect the different specifications in terms of out-of-band spurious emission. Focusing on the TX path of a UMTS/DCS1800 mobile phone, we propose hereinafter an efficient method aiming at synthesizing a complex 5th-order DeltaSigma modulator which respects the targeted standards spurious specifications. The use of a complex noise transfer function allows a better optimization of noise shaping. In addition, this approach eases the reconfiguration of the modulator, and, it is a powerful tool for all order (real and complex) DeltaSigma modulators synthesis, as it will be illustrated.