A 2.5-3.125-Gb/s quad transceiver with second-order analog DLL-based CDRs (original) (raw)

2005, IEEE Journal of Solid-State Circuits

This paper describes a 2.5-3.125-Gb/s quad transceiver with second-order analog delay-locked loop (DLL)-based clock and data recovery (CDR) circuits. A phase-locked loop (PLL) is shared between receive (RX) and transmit (TX) chains. On each RX channel, an amplifier with user-programmable input equalization precedes the CDR. Retimed data then goes to an 1:8/1:10 deserializer. On the TX side, parallel data is serialized into a high-speed bitstream with an 8:1/10:1 multiplexer. The serial data is introduced off-chip through a high-speed CML buffer having single-tap pre-emphasis. Proposed DLL-based CDR can tolerate large frequency offsets with no jitter tolerance degradation due to its second-order PLL-like nature. Also, this study introduces an improved charge-pump and an improved phase-interpolator. Fabricated in a 0.15-m CMOS process, the 1.9-mm 2 transceiver front-end operates from a single 1.2-V supply and consumes 65-mW/channel of which 32 mW is due to the CDR. CDR jitter generation and high-frequency jitter tolerance are 5.9 ps-rms and 0.5 UI, respectively, for 3.125 Gb/s, 2 23 1 PRBS input data with 800-ppm frequency offset. Index Terms-Chip-to-chip communication, clock and data recovery (CDR), delay-locked loop (DLL), phase-locked loop (PLL), serial communication, transceivers. I. INTRODUCTION T HE ever increasing input/output (IO) bandwidth demand for high-speed interconnects for optical, backplane, and chip-to-chip communication necessitates high-throughput serial transceiver integrated circuits (ICs). To increase throughput, multiple (typically four or eight, and sometimes in excess of a hundred [1], [2]) 2.5-3.125-Gb/s serial transceivers are widely used in parallel. Low jitter, low power, and small area requirements are essential for integrated multichannel transceivers. In receivers where traditional phase-locked loop (PLL)-based CDRs are used, multi-VCO coupling and increased power dissipation and area are the main drawbacks. Digital [3]-[5] and analog [7]-[9] delay-locked loop (DLL)-based clock and data recovery (CDR) circuits, on the other hand, share a common PLL among multiple channels, thereby avoiding the aforementioned problems. DLLs based on digital phase interpolation have typically high jitter due to phase jumps caused by finite step resolution, especially when there is a frequency offset between data rate and reference frequency (asynchronous mode). Analog DLLs, compared to their digital counterparts, are more immune to the phase jump problem. Therefore, they