Low-voltage low-power CMOS full adder (original) (raw)

Implementation of Low Power CMOS Full Adders Using Pass Transistor Logic

The efficiency of a system mainly depends on the performance of internal components present in the system. The internal components should be designed in such a way that they consume low power with high speed. Lot of components is in circuits including full-adder. This is mainly used in processors. A new Pass transistor full adder circuit is implemented in this paper. The main idea is to introduce the design of high performance and based pass transistor full adders which acquires less area and transistor count. The high performance of pass transistor low power full adder circuit is designed and the simulation has been carried out on Tanner EDA Tool. The result shows that the proposed full adder is an efficient full adder cell with least MOS transistor count that reduces the high power consumption and increases the speed. In this paper CMOS full adder circuits are designed to reduce the power and area and to increase the speed of operation in arithmetic application. To operate at ultra-low supply voltage, the pass logic circuit that cogenerates the intermediate XOR and XNOR outputs has been improved to overcome the switching delay problem

LOW-POWER 1-BIT FULL-ADDER CELL USING ENHANCED PASS TRANSISTOR LOGIC AND POWER GATING

Adders have become one of the important components in the digital world, such that there exists no design without it. Adders are not only used for additions, but it is also one of the basic building blocks that have been used for many other functions such as subtractions, multiplications, and divisions etc. In the field of Very Large Scale Integration (VLSI), Adders are used as the basic component from processors to ASICs. Propagation delay, Power and Area are the acceptable Quality metrics of the designed products. Recent days has proved that the use of Complementary Pass Transistor Logic (CPL) and sleep transistor provides a drastic reduction in the power compared to CMOS logic. Power Gating is one such well known technique where a sleep transistor is added between actual ground rail and circuit ground. The device is turned off during sleep mode to cut-off the leakage path. This technique results in a substantial reduction in leakage at a minimal impact on performance. This paper has spread the focus on Low power Adder design based on PTLs, with reduced sub threshold leakage power consumption and ground bounce noise during sleep to active mode transition, thereby achieving 2.5% reduction in power without affecting other quality metrics of the design. The CPL design has been modeled and analyzed using TANNER EDA with TSMC MOSIS 250nm technology. In the present paper we will propose low leakage 1 bit CMOS full adder circuit in 90nm technology with supply voltage of 1V. Keywords: CPL, Power, VLSI, Adder

Low Power Full Adder Implementation Based Pass Transistor Technology

— Addition is a fundamental for all the arithmetic operation, it is mainly used in digital signal processing architecture and microprocessor. The sum module is the core of arithmetic operation, like subtraction, multiplication, division. The aim of the project is design of full adder having low power consumption and low power delay. In this project, a new hybrid 1-bit full adder is designed using both CMOS and pass transistor logic, for the purpose of reducing the no of transistors. It consists of three modules such as two XOR module and one MUX module. It is used to improving power delay product (PDP). This can be implemented by using the software Tanner EDA. Keywords— CMOS logic,MUX module, logic,Power delay product, Tanner EDA XOR module.

A novel low-power full-adder cell for low voltage

Integration, the VLSI Journal, 2009

This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the timeconsuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-mm CMOS process technology. The adder cell is compared with seven widely used adders based on power consumption, speed, power-delay product (PDP) and area efficiency. Intensive simulation runs on a Cadence environment and HSPICE show that the new adder has more than 11% in power savings over a conventional 28-transistor CMOS adder. In addition, it consumes 30% less power than transmission function adder (TFA) and is 1.11 times faster.

IRJET- DESIGN OF LOW POWER HIGH SPEED FULL ADDER CIRCUITS USING XOR- XNOR TOPOLOGY

IRJET, 2020

The explosive growth of battery operated portable applications such as cellular phones, smart cards, PDAs, laptops and the evolution of the shrinkage of the technology requires smaller silicon area, high throughput circuitry and most importantly low power. Power consumption of any system can be reduced by scaling the supply voltage and operating frequency. But, it increases the propagation delay of the system and degrade the driving capability of the design. Therefore, designing a full adder with improved power delay characteristics is of great interest. The greatest challenge in low power VLSI design is reduction of power dissipation. Novel circuits for XOR/XNOR and simultaneous XOR-XNOR functions are proposed. The proposed circuits are highly optimized in terms of the power consumption. The proposed circuits are investigated in terms of variations of the supply and threshold voltages, output capacitance, input noise immunity, and the size of transistors. The simulations are carried out in Tanner EDA tool.

Study of Design and Analysis of Low-Power 10-Transistor Full Adders Using Novel XOR–XNOR Gates

IOSR journal of VLSI and Signal Processing, 2014

Full adders are vital components in applications such as digital signal processors (DSP) architectures and microprocessors. In this paper, we propose a technique to build a total of 41 new 10-transistor FA using novel XOR and XNOR gates in combination with existing ones.We have done over ten thousand HSPICE simulation runs of the entire the different adders in different input patterns, frequencies, and load capacitances. Almost all those new adders consume less power in high frequencies, while 3 new adders consistently use on average 10% less power and have higher speed compared with the previous Ten-transistor full adder and the conventional 28-T CMOS adder. One draw back of the novel adders is the threshold-voltage loss of the pass transistors.

Analysis of Different CMOS Full Adder Circuits Based on Different Parameter for Low Voltage

International journal of engineering research and technology, 2018

The demand for portable consumer electronics products is increasing at extremely high rate in recent years; therefore development of low-power VLSI circuits is essential. To achieve this objective a lot of innovative work has been done in this field, many innovative designs for basic logic functions have appeared. Various adders are used for implementing these logic functions which are most important components in digital design. The performance of these full adders can be measured in terms of propagation delay, power dissipation and power delay product. In this paper the performance of eleven different 1-bit full adder cells based on different logic styles are evaluated. The framework includes evaluation performance of different logic styles including an input test pattern which are analyzed with respect to power, delay and power-delay product. Evaluating the performance of a full adder cell is categorized on the basis of three different types of analysis: 1. Comparison of full add...

DESIGN OF LOW-POWER FULL ADDER IN 0.18 µm CMOS TECHNOLOGY

With the increase in device integration level and the growth in complexity of Integrated circuits, small delay and low power dissipation become important parameters as these increases performance and portability. Battery storage is limited, to extend battery life; low power operation is the primary requirement in integrated circuits. Furthermore, high speed and multiple parallel applications need high computing power, placing greater demands on energy storage elements within the system. Large power dissipation in high performance digital systems requires large size heat sinks. These off chip component makes chip bulky and require large space. Secondly, extra heat in integrated circuit degrades the system performance. The full adder (FA) is a very important and basic building block in Arithmetic and Logic unit (ALU) of digital processor. The most widely accepted metrics to measure the quality of a digital circuit or to compare various circuit styles is power delay product. Further, Portability imposes a strict limitation on power dissipation while needs more computational speeds. The reduced power consumption and the improved speed require optimizations at all levels of the design procedure.

Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications

International Journal of Electronics, 2019

This paper presents a low power and high speed two hybrid 1-bit full adder cells employing both pass transistor and transmission gate logics. These designs aim to minimise power dissipation and reduce transistor count while at the same time reducing the propagation delay. The proposed full adder circuits utilise 16 and 14 transistors to achieve a compact circuit design. For 1.2 V supply voltage at 0.18-μm CMOS technology, the power consumption is 4.266 μW was found to be extremely low with lower propagation delay 214.65 ps and power-delay product (PDP) of 0.9156 fJ by the deliberate use of CMOS inver-ters and strong transmission gates. The results of the simulation illustrate the superiority of the newly designed 1-bit adder circuits against the reported conservative adder structures in terms of power, delay, power delay product (PDP) and a transistor count. The implementation of 8-bit ripple carry adder in view of proposed full adders are finally verified and was observed to be working efficiently with only 1.411 ns delay. The performance of the proposed circuits was examined using Mentor Graphics Schematic Composer at 1.2 V single ended supply voltage and the model parameters of a TSMC 0.18-μm CMOS. ARTICLE HISTORY

A novel adder cell for ultra low voltage, ultra low power networks in nanoscale VLSI circuits

IEICE Electronics Express, 2011

A novel full adder cell is designed so that it can overcome the challenges of circuit design in deep submicron (DSM) technology. The proposed adder cell utilizes multiplexing control input techniques (MCIT) for the sum operation and uses a new arrangement of pass transistors for carry operation. The adder is then used in an 8×8 bit Braun-array multiplier to show its performance. The layout of multiplier is simulated in 32 nm CMOS technology by Microwind31 (MW31) VLSI CAD TOOL. Simulated results show that our circuit operates properly in nanoscale and has a very small area.