Bias temperature instability model using dynamic defect potential for predicting CMOS aging (original) (raw)
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New Model for Simulating Impact of Negative Bias Temperature Instability (NBTI) in CMOS Circuits
2014
Negative Bias Temperature Instability (NBTI) is commonly seen in p-channel transistors under negative gate voltages at an elevated temperature. The interface traps, oxide traps and NBTI mechanisms are discussed and their effect on circuit degradation and results are discussed. This thesis focuses on developing a model for simulating impact of NBTI effects at circuit level. The model mimics the effects of degradation caused by the defects. The NBTI model developed in this work is validated and sanity checked by using the simulation data from silvaco and gives excellent results. Furthermore the susceptibility of CMOS circuits such as the CMOS inverter, and a ring oscillator to NBTI is investigated. The results show that the oscillation frequency of a ring oscillator decreases and the SET pulse broadens with the NBTI.
In this paper, the negative-bias temperature instability (NBTI) in p-type gate-all-around silicon nanowire MOSFETs (SNWTs) is investigated for circuit aging analysis. Several important features of NBTI in SNWTs are discussed, including the impacts of 2-D hydrogen diffusion, the nonuniform temperature profile caused by self-heating effects, the multiple crystallographic orientations of nanowire channel surface, the gate-trimming process-induced additional trapping effects, and the impacts of oxide hole trapping. A predictive NBTI model for SNWTs is proposed and adopted in circuit simulation to evaluate the performance degradations of typical logic and analog circuits, such as inverter, static random access memory cell, ring oscillator, and current mirror. Without considering other indirect factors, the results indicate that the performance degradation directly due to NBTI alone is relatively small, i.e., within the range of less than 8% degradation for the typical circuits simulated. However, the NBTI behavior in SNWTs is sensitive to process variations, which cause enhanced variability problem by inducing time-dependent threshold voltage fluctuations.
Mechanism of Dynamic Bias Temperature Instability in p- and nMOSFETs: The Effect of Pulse Waveform
IEEE Transactions on Electron Devices, 2000
The waveform effect on dynamic bias temperature instability (BTI) is systematically studied for both p-and nMOSFETs with ultrathin SiON gate dielectrics by using a modified direct-current current-voltage method to monitor the stress-induced interface trap density. Interface traps are generated at the inversion gate bias (negative for pMOSFETs and positive for nMOSFETs) and are partially recovered at the zero or accumulation gate bias. Devices under high-frequency bipolar stress exhibit a significant frequency-dependent degradation enhancement. proximate analytical expressions of the interface trap generation for devices under the static, unipolar, or bipolar stress are derived in the framework of conventional reaction-diffusion (R-D) model and with an assumption that additional interface traps (N * it ) are generated in each cycle of the dynamic stress. The additional interface trap generation is proposed to originate from the transient trapped carriers in the states at and/or near the SiO 2 /Si interface upon the gate voltage reversal from the accumulation bias to the inversion bias quickly, which may accelerate dissociation of Si-H bonds at the beginning of the stressing phase in each cycle. Hence, N * it depends on the interface-state density, the voltage at the relaxation (i.e., accumulation) bias, and the transition time of the stress waveform (the fall time for pMOSFETs and the rise time for nMOSFETs). The observed dynamic BTI behaviors can be perfectly explained by this modified R-D model. Index Terms-Bias temperature instability (BTI), direct-current current-voltage (DCIV), dynamic stress, interface states, interface trap generation, MOSFET, reaction-diffusion (R-D) model, reliability.
NBTI modeling in analog circuits and its application to long-term aging simulations
2014 IEEE International Integrated Reliability Workshop Final Report (IIRW), 2014
We propose a circuit-level modeling approach for the threshold voltage shift in PMOS devices due to the negativebias temperature instability (NBTI). The model is suitable for application in analog circuit design and reproduces the results of existing digital-stress NBTI models in the limit of two-level stress signals. It accounts for recovery effects during intervals of low stress, and it predicts a stress-pattern dependent saturation of the degradation at large operation times. Since the model can be solved numerically in an efficient way, we have direct access to the threshold voltage shift at arbitrary times, in particular to the exact solution at large operation times, without any approximation. We implement the model via the Cadence Spectre URI. Finally, we make use of the model to compare the aging properties of several analog stress patterns. We furthermore present the results of an analog circuit-level NBTI simulation of a ring oscillator.
Negative Bias Temperature Instability(NBTI) has become an important reliability concern for ultra-scaled Silicon IC technology with significant implications for both analog and digital circuit design. As the Integrated Circuits (IC) density keeps on increasing with the scaling of CMOS devices in each successive technology generation, stress analysis or reliability concerns mainly Negative Bias Temperature Instability (NBTI) becomes a major challenge. Stress Analysis becomes important for any digital circuit as it predicts the life time of the circuit in terms of the degradation of device parameters. NBTI degrades the performance of a PMOS transistor under a negative gate stress. The after effects of NBTI include: (a) threshold voltage increase of PMOS transistor, (b) drain current degradation, and (c) speed degradation. Elevated temperature and the negative gate stress play an important role in degradation of Gate Oxide. Before any circuit design Stress Analysis becomes important for any device in order to get the complete performance of the circuit. Negative bias temperature instability (NBTI) has become the dominant reliability concern for nanoscale PMOS transistors. In this paper basically we have studied the Stress Analysis and the impact of temperature of NBTI on a CMOS inverter circuit.
An Analytical Model for Negative Bias Temperature Instability
2006 IEEE/ACM International Conference on Computer Aided Design, 2006
Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a significant reliability concern in present day digital circuit design. With continued scaling, the effect of NBTI has rapidly grown in prominence, forcing designers to resort to a pessimistic design style using guard-banding. Since NBTI is strongly dependent on the time for which the PMOS device is stressed, different gates in a combinational circuit experience varying extents of delay degradation. This has necessitated a mechanism of quantizing the gate-delay degradation, to pave the way for improved design strategies. Our work addresses this issue by providing a procedure for determining the amount of delay degradation of a circuit due to NBTI. An analytical model for NBTI is derived using the framework of the Reaction-Diffusion model, and a mathematical proof for the widely observed phenomenon of frequency independence is provided. Simulations on ISCAS benchmarks under a 70nm technology show that NBTI causes a delay degradation of about 8% in combinational logic based circuits after 10 years ( ¿ ¢ ½¼ s).
Microelectronics Reliability, 2007
CMOS reliability is facing unprecedented challenges due to the continued scaling of device dimensions. To sustain the current scaling trends, it is imperative to understand the fundamental physics of failure mechanisms. Due to the inherent complexity of these mechanisms, some of the key failure mechanisms can be understood only by a numerical modeling approach. Most failure mechanisms have a characteristic time dependence to failure. Hence in this work, we use a numerical approach to investigate the time dependence of failure mechanism associated with interfacial kinetics at the Si/SiO 2 interface. Several models are critically examined to develop a reaction/diffusion based modeling framework for predicting interface state generation. Our modeling shows reactions at the Si/SiO 2 interface have a direct impact on the time dependence (or time slopes). These time kinetics predictions shed light on the underlying mechanisms behind an technologically important failure mechanism (negative bias temperature instability (NBTI)). In particular, the breaking of an interface SiH bond to release atomic H results in a time slope of 0.25, whereas the release of molecular H 2 results in a time slope of 0.165. Based on this model, we conclude NBTI degradation is dominated by diffusion of neutral molecular hydrogen defects. These models are extended to 2D simulations to study device layout effects. Our simulations suggest differences with device structure (Lgate, Width etc.) and agree with observed experimental results. The developed models are further applied to understand operation under dynamic and static stress.
Negative Bias Temperature Instability Studies for Analog Soc Circuits
2012
Fawnizu Azmadi Hussin, for their unwavering support and guidance over the last one and a half years throughout my graduate studies. Their insightful knowledge, comments and wisdom have proved to be invaluable to the completion of my Msc. degree and this thesis. I would like to thank Kevin Arendt of Intel Corporation for providing the thermal sensor circuit and extensive experience on analog circuits particularly the bandgap reference and for providing the sample circuits and reliability data used in this paper. This work is dedicated to my caring, loving and supportive wife, Dr. Ismaliza Ismail. Without her I could not have finished this journey and completed this thesis on a part time basis within one and a half years. Her genuine encouragement and understanding over the years have been invaluable. I would also like to thank the rest of my immediate and extended family for their emotional support throughout my graduate studies. Their endless support is crucial. v ABSTRACT Negative Bias Temperature Instability (NBTI) is one of the recent reliability issues in sub threshold CMOS circuits. NBTI effect on analog circuits, which require matched device pairs and mismatches, will cause circuit failure. This work is to assess the NBTI effect considering the voltage and the temperature variations. It also provides a working knowledge of NBTI awareness to the circuit design community for reliable design of the SOC analog circuit. There have been numerous studies to date on the NBTI effect to analog circuits. However, other researchers did not study the implication of NBTI stress on analog circuits utilizing bandgap reference circuit. The reliability performance of all matched pair circuits, particularly the bandgap reference, is at the mercy of aging differential. Reliability simulation is mandatory to obtain realistic risk evaluation for circuit design reliability qualification. It is applicable to all circuit aging problems covering both analog and digital. Failure rate varies as a function of voltage and temperature. It is shown that PMOS is the reliabilitysusceptible device and NBTI is the most vital failure mechanism for analog circuit in sub-micrometer CMOS technology. This study provides a complete reliability simulation analysis of the on-die Thermal Sensor and the Digital Analog Converter (DAC) circuits and analyzes the effect of NBTI using reliability simulation tool. In order to check out the robustness of the NBTI-induced SOC circuit design, a bum-in experiment was conducted on the DAC circuits. The NBTI degradation observed in the reliability simulation analysis has given a clue that under a severe stress condition, a massive voltage threshold mismatch of beyond the 2mV limit was recorded. Bum-in experimental result on DAC proves the reliability sensitivity of NBTI to the DAC circuitry.