A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays (original) (raw)

Defect and Variation Issues on Design Mapping of Reconfigurable Nanoscale Crossbars

2010 IEEE Computer Society Annual Symposium on VLSI, 2010

High defect density and extreme process variation for nanoscale self-assembled crossbar-based architectures have been expected to be as fundamental design challenges. Consequently, defect and variation issues must be considered on logic mapping on nanoscale crossbars. In this paper, we investigate a greedy algorithm for the variation and defect aware logic mapping of crossbar arrays. Based on Mont-Carlo simulation, we compare the proposed technique with other logic mapping techniques such as variation unaware and exhaustive search mapping in terms of accuracy as well as runtime. I.

On Finding a Defect-free Component in Nanoscale Crossbar Circuits

Procedia Computer Science, 2015

We propose a technique for the analysis of manufacturing yield of nano-crossbar architectures for different values of defect percentage and crossbar-size. We provide an estimate of the minimum-size crossbar to be fabricated wherein a defect-free crossbar of a given size can always be found with a guaranteed yield. Our technique is based on logical merging of two defective rows (or two columns) that emulate a defect-free row (or column). Experimental results show that the proposed method provides higher defect-tolerance compared to that of previous techniques.

A BIST Approach for Configurable Nanofabric Arrays

2008 8th IEEE Conference on Nanotechnology, 2008

This work proposes a Built-in Self Test (BIST) approach to test crossbars for a defined set of faults. The BIST can classify the different programmable elements in the crossbars as non-defective or defective with a certain fault type. The logic synthesis can then configure the crossbar by avoiding these defective elements.

Logic synthesis and testing techniques for switching nano-crossbar arrays

Microprocessors and Microsystems, 2017

Beyond CMOS, new technologies are emerging to extend electronic systems with features unavailable to silicon-based devices. Emerging technologies provide new logic and interconnection structures for computation, storage and communication that may require new design paradigms, and therefore trigger the development of a new generation of design automation tools. In the last decade, several emerging technologies have been proposed and the time has come for studying new ad-hoc techniques and tools for logic synthesis, physical design and testing. The main goal of this project is developing a complete synthesis and optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. New models for diode, FET, and four-terminal switch based nanoarrays are developed. The proposed methodology implements logic, arithmetic, and memory elements by considering performance parameters such as area, delay, power dissipation, and reliability. With combination of logic, arithmetic, and memory elements a synchronous state machine (SSM), representation of a computer, is realized. The proposed methodology targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories. The results of this project will be a foundation of nano-crossbar based circuit design techniques and greatly contribute to the construction of emerging computers beyond CMOS. The topic of this project can be considered under the research area of "Emerging Computing Mod

Integrated Synthesis Methodology for Crossbar Arrays

Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures - NANOARCH '18, 2018

Nano-crossbar arrays have emerged as area and power efficient structures with an aim of achieving high performance computing beyond the limits of current CMOS. Due to the stochastic nature of nano-fabrication, nano arrays show different properties both in structural and physical device levels compared to conventional technologies. Mentioned factors introduce random characteristics that need to be carefully considered by synthesis process. For instance, a competent synthesis methodology must consider basic technology preference for switching elements, defect or fault rates of the given nano switching array and the variation values as well as their effects on performance metrics including power, delay, and area. Presented synthesis methodology in this study comprehensively covers the all specified factors and provides optimization algorithms for each step of the process.

TECHNOLOGY MAPPING FOR CIRCUIT OPTIMIZATION USING CONTENT-ADDRESSABLE MEMORY by

2005

The growing complexity of Field Programmable Gate Arrays (FPGA's) is leading to architectures with high input cardinality look-up tables (LUT's). This thesis describes a methodology for area-minimizing technology mapping for combinational logic, specifically designed for such FPGA architectures. This methodology, called LURU, leverages the parallel search capabilities of Content-Addressable Memories (CAM's) to outperform traditional mapping algorithms in both execution time and quality of results. The LURU algorithm is fundamentally different from other techniques for technology mapping in that LURU uses textual string representations of circuit topology in order to efficiently store and search for circuit patterns in a CAM. A circuit is mapped to the target LUT technology using both exact and inexact string matching techniques. Common subcircuit expressions (CSE's) are also identified and used for architectural optimization-a small set of CSE's is shown to effectively cover an average of 96% of the test circuits. LURU was tested with the ISCAS'85 suite of combinational benchmark circuits and compared with the mapping algorithms FlowMap and CutMap. The area reduction shown by LURU is, on average, 20% better compared to FlowMap and CutMap. The asymptotic runtime complexity of LURU is shown to be better than that of both FlowMap and CutMap.

Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays

International Conference on Computer Aided Design, 2007

Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we suggest a way to reduce the decoder size and keep it defect tolerant by using multiple threshold voltages (VT), which is enabled by our underlying technology. We define two types of multi-valued decoders and

FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

… -Aided Design of Integrated Circuits and …, 1994

The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs. In the past a few years, a number of heuristic algorithms have been proposed for technology mapping in lookup-table (LUT) based FPGA designs, but none of them guarantees optimal solutions for general Boolean networks and little is known about how far their solutions are away from the optimal ones. This paper presents a theoretical breakthrough which shows that the LUT-based FPGA technology mapping problem for depth minimization can be solved optimally in polynomial time. A key step in our algorithm is to compute a minimum height Kfeasible cut in a network, which is solved optimally in polynomial time based on network flow computation. Our algorithm also effectively minimizes the number of LUTs by maximizing the volume of each cut and by several post-processing operations. Based on these results, we have implemented an LUT-based FPGA mapping package called FlowMap. We have tested FlowMap on a large set of benchmark examples and compared it with other LUT-based FPGA mapping algorithms for delay optimization, including Chortle-d, MIS-pga-delay, and DAG-Map.

An efficient approach for designing and minimizing reversible programmable logic arrays

Proceedings of the great …, 2012

Reversible computing dissipates zero energy in terms of information loss at input and also it can detect error of circuit by keeping unique input-output mapping. In this paper, we have proposed a cost effective design of Reversible Programmable Logic Arrays (RPLAs) which is able to realize multi-output ESOP (Exclusive-OR Sum-Of-Product) functions by using a cost effective 3×3 reversible gate, called MG (MUX Gate). Also a new algorithm has been proposed for the calculation of critical path delay of reversible PLAs. The minimization processes consist of algorithms for ordering of output functions followed by the ordering of products. Five lower bounds on the numbers of gates, garbages and quantum costs of reversible PLAs are also proposed. Finally, we have compared the efficiency of proposed design with the existing one by providing benchmark functions analysis. The experimental results show that the proposed design outperforms the existing one in terms of numbers of gates, garbages, quantum costs and delay.

Efficient CMOL Nanoscale Hybrid Circuit Cell Assignment Using Simulated Evolution Heuristic

Recently, many CMOS/nanodevices hybrid architectures have been proposed, the new architectures combine the flexibility and high fabrication yield advantages of CMOS technology with nanometer scale latching devices. CMOL, a novel architecture that uses two levels of perpendicular nano-wires as crossbar interconnection on top of inverter-based CMOS stack, offers significant density advantages and overcomes physical barriers of lithography-based fabrication. However, the confined connectivity of CMOL nanofabric to only cells that are located within proximity square-like con-nectivity domain, reduces the flexibility of VLSI design automation and further complicates cells placement. In this paper we use Simulated Evolution algorithm to solve the NP-hard problem of assigning NOR/INV gates to CMOL array. The main objective is to reduce the total number of buffers that must be inserted between cells that require long wires to connect. A novel goodness and allocation functions are introduced for efficient exploration of search space. Empirical results for ISCAS'89 benchmarks are compared with previous solutions using GA, MA, and LRMA heuristics. Our approach is able to find better solutions for all tested benchmarks and with 82% average reduction in CPU processing time.