FlexFi: A Flexible Fault Injection Environment for Microprocessor-Based Systems (original) (raw)
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EXFI: a low-cost fault injection system for embedded microprocessor-based boards
ACM Transactions on Design Automation of Electronic Systems, 1998
Evaluating the faulty behavior of low-cost embedded microprocessor-based boards is an increasingly important issue, due to their adoption in many safety critical systems. The architecture of a complete Fault Injection environment is proposed, integrating a module for generating a collapsed list of faults, and another for performing their injection and gathering the results. To address this issue, the paper describes a software-implemented Fault Injection approach based on the Trace Exception Mode available in most microprocessors. The authors describe EXFI, a prototypical system implementing the approach, and provide data about some sample benchmark applications. The main advantages of EXFI are the low cost, the good portability, and the high efficiency.
2015 Third International Conference on Technological Advances in Electrical, Electronics and Computer Engineering (TAEECE), 2015
Embedded microprocessors are widely used in most of the safety critical digital system applications. A fault in a single bit in the microprocessors may cause soft errors. It has different affects on the program outcome whether the fault changes a situation in the application. In order to analyse the behaviour of the applications under the faulty conditions we have designed a custom verification system. The verification system has two parts as Field Programmable Gate Array (FPGA) and personnel computer (PC). We have modified Natalius open source microprocessor in order to inject stuck-at-faults into it. We have handled a fault injection method and leveraged it to increase randomness. On FPGA, we have implemented modified Natalius microprocessor, the fault injection method and the communication protocol. Then the "Most Significant Bit First Multiplication Algorithm" has been implemented on the microprocessor as an application. We have prepared an environment which sends inputs to and gets outputs from the Natalius microprocessor on PC part. Finally, we have analysed our application by injecting faults in specific location and random location in register file to make some classifications for effects of the injected faults.
On Enhancing Fault Injection's Capabilities and Performances for Safety Critical Systems
2014 17th Euromicro Conference on Digital System Design, 2014
The increasing need for high-performance dependable systems with and the ongoing strong cost pressure leads to the adoption of commercial off-the-shelf devices, even for safety critical applications. Ad hoc techniques must be studied and implemented to develop robust systems and to validate the design against all safety requirements. Nonetheless, white-box fault injection relies on the deep knowledge of the system hardware architecture and it is seldom available to the designer. Furthermore it would require enormous simulation time to be carried out. This work presents an enhanced architecture for fast fault injection to be used for design-time coverage evaluation and runtime testing. A test case will be presented on Xilinx Zynq system on programmable chip, suitable for design-time diagnostic coverage evaluation and online testing for safety-critical systems resorting to the proposed fault injection methodology.
Using run-time reconfiguration for fault injection applications
2003
The probability of faults occurring in the field increases with the evolution of the CMOS technologies. It becomes, therefore, increasingly important to analyze the potential consequences of such faults on the applications. Fault injection techniques have been used for years to validate the dependability level of circuits and systems, and approaches have been proposed to analyze very early in the design process the functional consequences of faults. These approaches are based on the high-level description of the circuit or system and classically use simulation. Recently, hardware emulation on FPGA-based systems has been proposed to accelerate the experiments; in that case, an important characteristic is the time to reconfigure the hardware, including re-synthesis, place and route, and bitstream downloading. In this paper, an alternative approach is proposed, based on hardware emulation and run-time reconfiguration. Fault injection is carried out by direct modifications in the bitstream, so that re-synthesizing the description can be avoided. Moreover, with some FPGA families (e.g., Virtex or AT6000), it is possible to reconfigure the hardware partially at run-time. Important time-savings can be achieved when taking advantage of these features, since the injection of a fault necessitates the reconfiguration of only a few resources of the device. The injection process is detailed for several types of faults and experimental results are discussed.
LDSFI: a Lightweight Dynamic Software-based Fault Injection
2019 9th International Conference on Computer and Knowledge Engineering (ICCKE)
Recently, numerous safety-critical systems have employed a variety of fault tolerance techniques, which are considered an essential requirement to keep the system faulttolerant. While the current trend in processors technology has increased their effectiveness and performance, the sensitivity of processors to soft errors has increased significantly, making their fault tolerance ability questionable. In this context, fault injection is considered as one of the most popular, rapid, and cost-effective techniques which enables the designers to assess the fault tolerance of systems under faults before their deployment. In this paper, a pure software fault injection technique called LDSFI (a Lightweight Dynamic Software-based Fault Injection) is presented and evaluated. Due to the dynamic aspect of LDSFI, faults are automatically injected into binary code at runtime. Thereby, the proposed technique does not impose any program runtime overhead since the intended source code is not required. The effectiveness of LDSFI was validated through performing exhaustive fault injection experiments using well-known benchmarks. The experiments were carried out using a Core 2 Duo processor, as an Intel x86 Dual-Core PC with 4GB RAM running Ubuntu Linux 14.04 with the GNU Compiler Collection (GCC) version 4.9. Since LDSFI relies on the GNU, it is highly portable and can be adapted for different platforms.
A Simulated Fault Injection Framework for Time-Triggered Safety-Critical Embedded Systems
This paper presents a testing and simulated fault injection framework for time-triggered safety-critical embedded systems. Our ap-proach facilitates the validation of fault-tolerance mechanisms by per-forming non-intrusive Simulated Fault Injection (SFI) on models of the system at different stages of the development, from the Platform Inde-pendent Model (PIM) to the Platform Specific Model (PSM). The SFI enables exercising the intended fault tolerance mechanisms by injecting faults in a simulated model of a system. The main benefit of this work is that it enables an early detection of design flaws in fault-tolerant sys-tems, what reduces the possibility of late discovery of design pitfalls that might require an expensive redesign of the system. We examine the fea-sibility of the proposed approach in a case study, where SFI is used to assess the fault tolerance mechanisms designed in a simplified railway signaling system.
Codesign and Simulated Fault Injection of Safety-Critical Embedded Systems Using SystemC
2010 European Dependable Computing Conference, 2010
The international safety standard IEC-61508 highly recommends fault injection techniques in all steps of the development process of safety-critical embedded systems, in order to analyze the reaction of the system in a faulty environment and to validate the correct implementation of fault tolerance mechanisms. Simulated fault injection enables an early dependability assessment that reduces the risk of late discovery of safety related design pitfalls and enables the analysis of fault tolerance mechanisms at each design refinement step using techniques such as failure mode and effect analysis.