Analysing NBTI Impact on SRAMs with Resistive Defects (original) (raw)

Analyzing NBTI impact on SRAMs with resistive-open defects

2016 17th Latin-American Test Symposium (LATS), 2016

Density's increase in Static Random Access Memory (SRAM) has become an important concern for testing, since new types of defects that may occur during the manufacturing process are generated. In parallel, the increasing need to store more and more information has resulted in SRAMs that occupy the greatest part of Systems-on-Chip (SoCs). On the one hand, these manufacturing defects may lead to dynamic faults, considered one of the most important causes of test escape in deep-submicron technologies. On the other hand, the SRAM's robustness is considered crucial, since it may affect the entire SoC. In this context, one of the most important phenomena to degrade SRAM reliability is related to Negative-Bias Temperature Instability (NBTI), which causes memory cells' aging. In this context, the paper proposes to analyze the impact of NBTI in SRAM cells with weak resistive-open defects that can escape manufacturing test due to their dynamic behavior and, with aging, may become dynamic faults over time. The proposed combined analysis has been performed using SPICE simulations adopting a commercial 65nm CMOS technology library.

Impact of NBTI/PBTIon SRAMs within microprocessor systems: Modeling, simulation, and analysis

Microelectronics Reliability, 2013

A framework is proposed to analyze the impact of negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on memories embedded within state-of-art microprocessors. Our methodology finds the detailed electrical stress and temperature of each SRAM cell within a memory, embedded within a system running a variety of standard benchmarks. We study DC noise margins in conventional 6T SRAM cells as a function of NBTI/PBTI degradation and provide insights on memory reliability under realistic use conditions.

A Review of NBTI Degradation and its Impact on the Performance of SRAM

International Journal of Modern Education and Computer Science, 2016

Temporal degradation of VLSI design is a major reliability concern for highly scaled silicon IC technology. Negative Bias Temperature Instability (NBTI) in particular is a serious threat affecting the performance of both digital and analog circuits with time. This paper presents a review of NBTI degradation, its mechanism and various factors that affect the degradation caused by NBTI. Reaction Diffusion (RD) model based analytical expressions developed by various researchers are also discussed along with their features and underlying assumptions. Degradation in the Static RAM (SRAM) performance caused by NBTI is also discussed in detail along with the strategies that are employed to combat the effect of NBTI degradation in SRAM. Results of the review done for SRAM cell under NBTI degradation suggests that these design strategies are effective in improving the SRAM cell performance.

Impact of NBTI on SRAM Read Stability and Design for Reliability

Proceedings of the 7th …, 2006

Negative Bias Temperature Instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious effects on transistor threshold voltage. The degradation of PMOS devices due to NBTI leads to reduced temporal performance in digital circuits. We have analyzed the impact of NBTI on the read stability of SRAM cells. The amount of degradation in Static Noise Margin (SNM), which is a measure of the read stability of the 6-T SRAM cell has been estimated using Reaction-Diffusion (R-D) model. We propose a simple solution to recover the SNM of the SRAM cell using a data flipping technique and present the results simulated on BPTM 70nm and 100nm technology. We also compare and evaluate different implementation methodologies for the proposed technique.

Performance degradation of SRAM cells due to NBTI effects

2015

Ab stract—SRAM cells play an important role in today’s world and the impact they have on memory designs is tremendous. Different types of SRAM cells have been designed till date but consistent efforts are still being made to look out for ways to improve their performance. One such thing that affects the performance of the SRAM cells is the NBTI (Negative Bias Temperature Instability). This paper uses a simple 6T SRAM cell to see what exactly NBTI does to these cells and what happens as a result of the same. This paper explains more about what NBTI actually is, how does it arise, how do they change the device behavior or characteristics and what exactly happens to these SRAM cells on account of this effect. Also, apart from the effect of the NBTI on SRAM cells, this paper also shows the leakage current that persists in the SRAM cell while the entire circuit is switched off (standby mode).

Investigating the use of an on-chip sensor to monitor NBTI effect in SRAM

2012 13th Latin American Test Workshop (LATW), 2012

Today, the increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy the greatest part of a System-on-Chip (SoC). Therefore, SRAM's robustness is considered crucial to guarantee the reliability of such SoCs over lifetime. In this context, one of the most important phenomena degrading nano-scale SRAMs reliability is related to Negative-Bias Temperature Instability (NBTI). This paper proposes a new approach based on an On-Chip Aging Sensor (OCAS) to detect SRAM aging during system lifetime. The sensor is able to detect any specific aging state of a cell in the SRAM array. The strategy is based on the connection of an OCAS per SRAM column, which periodically performs off-line testing by monitoring write operations into the SRAM cells to detect aging. The approach is application-transparent since it is does not change the SRAM contents after testing. To prevent OCAS from aging by one side and from dissipating static...

An On-Chip Sensor to Monitor NBTI Effects in SRAMs

Journal of Electronic Testing, 2014

The increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy the greatest part of Systems-on-Chip (SoCs). Therefore, SRAM's robustness is considered crucial in order to guarantee the reliability of such SoCs over lifetime. In this context, one of the most important phenomena that degrades Nano-Scale SRAMs reliability is related to Negative-Bias Temperature Instability (NBTI), which causes the memory cells aging. The main goal of this paper is to present a hardware-based approach able to monitor SRAMs' aging during the SoC's lifetime based on the insertion of On-Chip Aging Sensors (OCASs). In more detail, the proposed strategy is based on the connection of one OCAS to every SRAM column, each periodically monitoring write operations on the SRAM cells. It is important to note that in order to prevent the OCAS from aging and to reduce leakage power dissipation, the OCAS circuitry is powered-off during its idle periods. The proposed hardware-based approach has been evaluated throughout SPICE simulations using 65 nm CMOS technology and the results demonstrate the sensor's capacity to detect early aging states and therefore, guaranteeing high SRAM reliability. To conclude, a complete analysis of the sensor's overheads is presented.

Countermeasures against NBTI degradation on 6T-SRAM cells

In current process technologies, NBTI (negative bias temperature instability) has the most severe aging effect on static random access memory (SRAM) cells. This degradation effect causes loss of stability. In this paper countermeasures against this hazard are presented and quantified via simulations in 90 nm process technologies by the established metrics SNM read , SNM hold , I read and Write Level. With regard to simulation results and practicability best candidates are chosen and, dependent on individual preferences at memory cell design, the best countermeasure in each case is recommended. 1 Motivation The ongoing miniaturization in modern CMOS technologies leads to a more and more challenging SRAM design: during read operation the cell must not flip to prevent data loss. During write operation the memory cell must flip to write new data in the cell. Thus there is only a certain area, where both a reliable read and write operation is possible. On top of variations, degradations are making this area smaller. To illustrate the effect of variations and degradations on SRAM cells, a Monte Carlo analysis was performed (Fig. 1). In this analysis 10 5 SNM read simulations (Seevinck et al., 1987) are performed for 0.4 V < V DD < 1.2 V: the transistors are exposed to variations (based on measured σ values), then −50 mV NBTI degradation is added to one pullup transistor. This represents a realistic worst case, as the expected end-of-life shift after 10 years at 1.32 V and 125 • C is −31 mV. Counting the number of not functional SRAM cells (SNM read < 0) the yield (fraction of functional memory cells) is determined. For the 256 Bit SRAM array it is assumed that the failure of one cell leads to the failure of the whole array. When the cells are only influenced by varia-Correspondence to: E. Glocker (elisabeth.glocker@tum.de) tions, the yield of the 256 Bit SRAM array decreases rapidly below V D,min = 0.75 V. To design functional SRAM arrays despite variations, different assist techniques have been developed. In contrast to variations, degradations occur with increasing magnitude during operating time. The V DD,min value, where the yield of the 256 Bit array starts to decrease, rises from 0.75 V to V D,min = 0.8 V when the SRAM array is exposed to variations plus −50 mV NBTI degradation. So V D,min is increased by approx. V th. V D,min would rise more if additional other degradations and/or a higher NBTI degradation were taken into account. As a result, countermeasures against NBTI are necessary to guarantee long-time operational SRAM cells. One first countermeasure is e.g. the Guard Band (Sect. 3.4), where V DD is limited to a value above V D,min to assure that the cell is not operated with a V DD with a high failure probability after degradation. After describing the consequences of the NBTI degradation on the SRAM cell in Sect. 2, countermeasures against NBTI degradation are presented (Sect. 3) and the best candidates in terms of simulation results and practicability are chosen and compared to each other (Sect. 4). Depending on the individual preferences at memory cell design, the best countermeasure in each case is recommended. 2 Consequences of NBTI degradation on 6T-SRAM memory cells BTI (bias temperature instability) degradation distinguishes between PBTI (positive BTI) and NBTI (negative BTI) degradation. NBTI affects pMOS transistors with nega-tiv potential on the gate referred to the potential on source and drain (Fig. 2). NBTI weakens pMOS transistor: Positive charges arise in the gate oxide and the absolute threshold voltage | V th | rises. It is harder to turn the transistor on. NBTI can be modeled with a rise of | V th | by V th. PBTI influences nMOS transistors with high-k gate oxide, thus in process technologies under 65 nm. So NBTI has the most damaging effect for current technologies (Drapatz et al., 2009a). Published by Copernicus Publications on behalf of the URSI Landesausschuss in der Bundesrepublik Deutschland e.V.

Analysis of SRAM metrics for data dependent BTI degradation and process variability

Integration, 2020

Bias Temperature Instability (BTI) is one of the most crucial reliability issues in modern CMOS technology. It leads to shift in device parameters, which eventually affect circuit performance. SRAM is a widely used circuit which occupies a considerable area in microprocessors. Hence it is important to understand the impact of BTI on performance/stability of SRAM. As device degradation due to BTI depends on gate activity, SRAM performance strongly depends on the data stored in the cell. In this paper, the gate activity is incorporated by activity factor 'α' which takes into account the various data patterns stored in the cell. Although many studies have reported the impact of BTI on SRAM performance, none focused on the worst degradation scenario. Our analysis with varying activity factor 'α' provides an opportunity to identify the data pattern for worst case degradation. Shift in threshold voltage due to BTI is modelled according to continuous and non-continuous applied gate bias, using physics-based compact model. Process variability is incorporated using Monte Carlo (MC) simulations and worstcase degradation at distribution tail is identified. In this paper, we consolidate various SRAM performance metrics from literature over the last three decades and demonstrate the impact of BTI and process variability with activity factor 'α' on these metrics.