Models and algorithms for bounds on leakage in CMOS circuits (original) (raw)
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Leakage power bounds in CMOS digital technologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002
The estimation of maximum and minimum leakage consumption for nominal values of the processing parameters is addressed. Tight upper and lower bounds of both extremes are found. In addition, input vectors producing a consumption close to these extremes are obtained. To solve this NP-complete problem, a new hierarchical method based on automatic test pattern generation (ATPG) tools is proposed. The
Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment
2002
Static power dissipation due to leakage current in transistors constitutes an increasing fraction of the total power in modern semiconductor technologies. Current technology trends indicate that the leakage contribution will increase rapidly. Developing power efficient products will require consideration of static power in early phases of design development. Design houses that use RTL synthesis based flow for designing ASICs require a quick and reasonably accurate estimate of static power dissipation. This is important for making early packaging decisions and planning the power grid. Keeping this in view, we propose a simple model which enables estimation of static power early in the design phase. Our model is based on the experimental data obtained from simulations at the design level: ln P leak lib = S lib ln Cells + C lib , where S lib and C lib are the technology-dependent slope and intercept parameters of the model and "Cells" is the number of cells in the design. The model is validated for a large benchmark circuit and the leakage power predicted by our model is within 2% of the actual leakage power predicted by a popular tool used in the industry.
Statistical analysis of subthreshold leakage current for VLSI circuits
IEEE Transactions on Very Large Scale Integration Systems, 2004
We develop a method to estimate the variation of leakage current due to both intra-die and inter-die gate length process variability. We derive an analytical expression to estimate the probability density function (PDF) of the leakage current for stacked devices found in CMOS gates. These distributions of individual gate leakage currents are then combined to obtain the mean and variance of the leakage current for an entire circuit. We also present an approach to account for both the inter-and intra-die gate length variations to ensure that the circuit leakage PDF correctly models both types of variation. The proposed methods were implemented and tested on a number of benchmark circuits. Comparison to Monte Carlo simulation validates the accuracy of the proposed method and demonstrates the efficiency of the proposed analysis method. Comparison with traditional deterministic leakage current analysis demonstrates the need for statistical methods for leakage current analysis.
Techniques for Sub-threshold Leakage Reduction in Low Power CMOS Circuit Designs
International Journal of Computer Applications, 2014
Power dissipation is a key consideration in the design of nano-scale CMOS VLSI circuits. Various techniques have been proposed for reduction of leakage in CMOS transistors. As the technology is emerging power dissipation due to leakage current has become a major contributor of total power consumption in the integrated devices. For high performance and device reliability, reduction of power consumption is highly desirable. Thus the importance of low power circuits has increased currently. The trend of scaling down has led to the increase in sub threshold leakage current and hence static power consumption. In this paper the different leakage reduction techniques for deep submicron technologies are focused comprehensively. The predominating sub threshold leakage current problem can be overcome by techniques like stacking of transistors, power gating, optimal body bias voltage generation at the circuit level thus providing a large range of choices for low-leakage power VLSI designers. .
Leakage Models for High Level Power Estimation
Leakage currents are one major concern when designing recent CMOS devices, making design for leakage at all stages of the design process mandatory. Early leakage optimization requires early leakage prediction, and for electronic system level design, this means estimation capabilities at register transfer (RT) level or above. Existing models are very accurate, but slow [transistor level such as Berkeley Simulator (BSIM)], or the slightly faster gate level models (such as the Liberty library), disregard relevant parameters. We present RT level leakage macro models, which are faster than recent gate level models, while preserving the accuracy of the transistor level models to a great extent. An estimation framework is proposed, describing the subthreshold, gate, and junction leakage of recent technology devices. The models are characterized using BSIM compact models and a Monte Carlo process variation description. Each varying BSIM parameter can be described. As an example of use, channel length, oxide thickness, and channel doping are regarded together with the temperature, supply voltage and body voltage. The final macro model needs less than a hundred parameters to capture the leakage behavior of an entire RT component and is still analytically describing the dependence to the process parameters. Compared to SPICE + BSIM, a model prediction is computed up to a hundred times faster for large RT components, and is, depending on the analyzed technology, within 2.1% (for 16-nm LP)-6.8% (for 65-nm bulk) deviation over a wide range of operating conditions and process variation settings.
A Perspective of Gate-Leakage Reduction in Deep SubMicron Ics
2012
Before the CMOS process is scaled into deep sub-micron process, dynamic energy loss has always dominated power dissipation, while leakage power is little. The aggressive scaling of device dimensions and threshold voltage has significantly increased leakage current exponentially, thus the MOS devices will no longer be totally turned-off anymore. The power dissipation caused by leakage current can’t be neglected anymore, which attracts extensive attentions. Based on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones, it is used for designing circuit for reducing gate leakage power. Series of iterative steps are carried out to find the design perspective effect in different technologies.
A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage
IEEE International Symposium on Circuits and Systems, 2004
Leakage power reduction is extremely important in the design of scaled CMOS logic circuits. The dominant leakage mechanism of such circuits is the gate leakage. This paper first describes a fast leakage estimation technique based on biasing states for both gate leakage and sub-threshold leakage. Next, it describes a leakage reduction method based on the selective insertion of control points.
Leakage in Nanometer Scale CMOS Circuits
High leakage current in deep sub-micron regimes is a significant contributor to the power dissipation of CMOS circuits as the CMOS technology scales down. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low power applications. . This paper explores transistor leakage
Leakage Reduction Onofic Approach For Deep Submicron Vlsi Circuits Design
2014
Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance of portable systems. Number of leakage reduction techniques employed to reduce the leakage current in deep submicron region but they have some trade-off to control the leakage current. ONOFIC approach gives an excellent agreement between power dissipation and propagation delay for designing the efficient CMOS logic circuits. In this article ONOFIC approach is compared with LECTOR technique and output results show that ONOFIC approach significantly reduces the power dissipation and enhance the speed of the logic circuits. The lower power delay product is the big outcome of this approach and mak...
International Journal of Engineering Applied Sciences and Technology
The trend of process scaling for CMOS technology has made subthreshold leakage reduction a growing concern for submicron circuit designers. Power consumption has become a principle design consideration as device sizes decrease and many more devices fit on a single chip. Since switching power is proportional to the square of the supply voltage, v 2 dd, new processes are tailored for lower supply voltages. The decrease in Vdd slows down devices, which requires that the threshold voltage, Vth, must be lowered to maintain performance. This reduction of Vth produces the exponential increase of subthreshold leakage currents. This research demonstrates a process used to model and optimize subthreshold leakage current for a CMOS device during its standby mode (OFF-state). The process involves the use of MATHCAD to examine the OFF-state subthreshold leakage current, Isub (OFF), based on variations in the threshold voltage, Vth, the effective transistor channel length, L, and the effective transistor channel width, W. The theoretical work entails simplifying the empirical relationship between the surface inversion potential, φs, the gate-source voltage, Vgs, and the subthreshold swing coefficient, n. This results in an expression relating the OFF-state subthreshold leakage current, Isub (OFF), the threshold voltage, Vth, the effective transistor channel length, L, and the effective transistor channel width, W. Analyzing the resulting equation using MATHCAD confirms that the off-state subthreshold leakage current, Isub (OFF) increases exponentially with a decrease in the threshold voltage, Vth, and linearly with a decrease in the effective transistor channel length, L. The results also show that the OFF-state subthreshold leakage current, Isub (OFF), increases linearly with the effective transistor channel width, W. The optimization process resulted in the values of Vth = 140 mV, L = 28 nm and w= 7 nm which give the desired outcome of greatly reduced off-state subthreshold leakage current, Isub (OFF) = 0.125 nA, for a single transistor.