20-Bit RISC and DSP System Design in an FPGA (original) (raw)
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IJERT-FPGA Based RISC and DSP System Design
International Journal of Engineering Research and Technology (IJERT), 2014
https://www.ijert.org/fpga-based-risc-and-dsp-system-design https://www.ijert.org/research/fpga-based-risc-and-dsp-system-design-IJERTV3IS20559.pdf Nowadays most of the microprocessor and microcontroller designs are based on Reduced Instruction Set Computer (RISC) core and many operations such as Discrete Cosine transform (DCT), Inverse DCT, Discrete Fourier Transform (DFT) and Inverse Discrete Fourier Transform (IDFT) are performed by DSP system. The concept of RISC architecture involves an attempt to reduce execution time by simplifying the instruction set of the computer and a Digital Signal Processor is a specialized microprocessor with an architecture developed for the fast operational needs of digital signal processing. A RISC (Reduced Instruction Set Computer) and DSP system which can perform Arithmetic, Logic and DSP operations are proposed. The processor use a 4 bit opcode and it can perform 15 different operations which include Arithmetic, Logic and DSP operations like DCT, IDCT, DFT & IDFT. The RISC machine fetches an instruction from memory. The instruction is 20 bit out of which 0-3 bits represent an opcode which decide the operation to be performed, 4-11 and 12-19 bits represent the registers holding the values to be used for the instructions. The output is of 8 bit value. The coding is done in VHDL language, synthesized using Xilinx ISE 13.2 and simulated using ISim.
A FPGA Implementation of a RISC Processorfor Computer Architecture
Ijca Proceedings on National Conference on Innovative Paradigms in Engineering and Technology, 2012
This paper is concerned with the design and implementation of a 32bit Reduced Instruction Set Computer (RISC) processor on a Field Programmable Gate Arrays (FPGAs). We are designing the processor with VHDL and the simulation using Altera Quartus Plus2, and we will implement on Altera cyclone II in FPGA.The test bench waveforms for the different parts of the processor are presented and the system architecture is demonstrated.
Implementation of RISC Microprocessor for DSP Systems
This paper is about the reduced instruction set computer (RISC), microprocessor CPU design that flavors a smaller and simpler set of instruction. In this project we have described 16-bit pipelined RISC processor for applications such as in real time digital signal processor and embedded systems. The processor designed specifically for DSP systems such as FFT, DWT, Convolution and ALU, executes most of instructions in a single cycle; conventional processors usually performs only arithmetic and mathematical operations. Hence RISC processors have complex control system which requires more clock cycle to operate, thus we overcome this problem using pipelined architecture of 4 stages i.e fetch, decode, execute and write back. In fact compared to base paper the area is reduced and speed is increased. The Simulation is done on XILINX 14.5i tool, implemented on SPARTAN-6 kit. Over all speed is achieved and results are verified. Keywords: Reduced instruction set computer(RISC), Digital Signal Processor (DSP), Fast Fourier Transform(FFT), Discrete wavelet transform(DWT), VHDL ________________________________________________________________________________________________________
Implementation of RISC System in FPGA
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This paper represents the combination of Reduced Instruction Set Computer (RISC) system using VHDL and implement. This paper presents a RISC processor designing to achieve various arithmetic operations. The RISC is a 20 bit processor. KeywordsArithmetic Logic(AL), Central Processing Unit(CPU), Control Unit(CU), Field Programmable Logic Array(FPGA), General Purpose Register(GPR), Program Counter(PC) Instruction Register(IR), , Reduced Instruction Set Computer(RISC), Register Set(RS), Configurable Logic Blocks (CLBs)
International Journal of Reconfigurable and Embedded Systems (IJRES), 2023
In this paper, a novel reduced instruction set computer (RISC)communication processor (RCP) has been designed with 32-bit operations which access 64-bit instruction format and implemented using field programmable gate array (FPGA). The design of the RISC processor is facilitated with communication operations like basic signals sine, cosine, and square, and modulation schemes like amplitude modulation, amplitude shift keying, analog, and digital quadrature amplitude modulation. Additionally, application-oriented operations like a traffic light, digital clock, and linear feedback shift register are included in the design. The pipeline mechanism is incorporated in the design to enhance the performance characteristics of the processor, hence allowing the execution of the instructions more effectively. Also, the design is implemented with Xilinx Virtex 7 family FPGA. The device utilization analysis of the proposed FPGA along with different FPGA families is evaluated and compared.
Design and Implementation of a 32bit RISC Processor on Xilinx FPGA
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Comparative Study of Different Methods Using FPGA Implementation of RISC Processor
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RISC Implementation Of Digital IIR Filter in DSP
This paper is base on the implementation of Reduce Instruction set computer with the application of Discrete Cosine transform (DCT) , Inverse DCT, Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT), Digital filter are performed by DSP system. Digital filter is one of the important contents of digital signal process. The performance of the processor design is improved by using the pipeline approach. It allows the processor to work on different steps of the instruction at the same time, thus more instruction can be executed in a shorter period of time. The analysis of this processor will provide various features including arithmetic operations. The speed of operation is mainly affected by the computational complexity due to multipliers and adder modules of the digital systems. Our work will targets the computer architecture courses and presents an FPGA (Field Programmable Gate Array) implementation of a MIPS (Microprocessor without Interlocked Pipeline Stages) via VHDL (Very high speed integrated circuit Hardware Description Language) design. The latency and computational time is utmost important in microprocessor. Thus we design the multiplier and adder module with improve latency and computational time.
Reduced Area and Low Power Implementation of FFT/IFFT Processor
Iraqi Journal for Electrical and Electronic Engineering, 2018
The Fast Fourier Transform (FFT) and Inverse FFT(IFFT) are used in most of the digital signal processing applications. Real time implementation of FFT/IFFT is required in many of these applications. In this paper, an FPGA reconfigurable fixed point implementation of FFT/IFFT is presented. A manually VHDL codes are written to model the proposed FFT/IFFT processor. Two CORDIC-based FFT/IFFT processors based on radix-2and radix-4 architecture are designed. They have one butterfly processing unit. An efficient In-place memory assignment and addressing for the shared memory of FFT/IFFT processors are proposed to reduce the complexity of memory scheme. With "in-place" strategy, the outputs of butterfly operation are stored back to the same memory location of the inputs. Because of using DIF FFT, the output was to be in reverse order. To solve this issue, we have re-use the block RAM that used for storing the input sample as reordering unit to reduce hardware cost of the proposed processor. The Spartan-3E FPGA of 500,000 gates is employed to synthesize and implement the proposed architecture. The CORDIC based processors can save 40% of power consumption as compared with Xilinx logic core architectures of system generator.