Reliability of soldered joints in CSPs of various designs and mounting conditions (original) (raw)

2001, IEEE Transactions on Components and Packaging Technologies

The chip size package (CSP) is being used in various portable electronic products recently. Further evaluation of the reliability of its soldered joints is required all the more now because those soldered joints are invisible. This study focused on the thermal fatigue life of soldered joints in the CSP. CSPs were mounted on printed circuit boards (PCBs) in various configurations and mounting conditions, and underwent thermal cycle testing. Then, the fatigue lives of their soldered joints were compared. As a result, the following two facts became apparent. First, reflowing at a 210 C peak tends to result in failures that may be derived from poor wetting between solder and pad, in cases where the CSP is mounted on a nickel and gold plated pad. And second, the size of the soldered joint has a great influence on its fatigue life. The larger the soldered joints that we made, the longer fatigue life they indicated. A finite element method (FEM) analysis of those mounted structures was also executed. Viscoplastic (creep and plastic) property of solder was evaluated to compute equivalent inelastic strain occurring in the joints. A parameter in the Coffin-Manson equation is obtained from the computed inelastic strain amplitudes and the experimented actual fatigue lives. This result will enable estimation of the fatigue life of soldered joints of the CSP without actual tests. Index Terms-CSP, FEM analysis, Ni/Au plated pad, reliability, thermal fatigue, Weibull cumulative hazard analysis. I. INTRODUCTION T HE chip size package (CSP) is now becoming one of the main products in the integrated circuit (IC) industry. In recent years, portable electronic products, such as cellular phones, camcorders, and pagers, have been required to be miniaturized, with increased performance. Accordingly, IC packages adopted in these electronic products are gradually being changed. The conventional IC package has outer leads lining its sides only, as seen in the quad flat package (QFP), small outline package (SOP), and so on. However, new types have external terminals arranged on their whole bottom surface, as seen in the ball grid array (BGA) and CSP.