Realization of Physical Downlink Control Channel (PDCCH) for LTE under SISO Environment using PlanAhead Tool and Virtex 5 FPGA (original) (raw)
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International Journal of Wireless and Mobile Computing, 2013
A combined architecture of Long Term Evolution (LTE) downlink data channels with optimised transmitter and receiver is proposed in this paper. This work mainly focuses on the downlink physical channels namely Physical Downlink Shared Channel (PDSCH), Physical Broadcast Channel (PBCH) and Physical Multicast Channel (PMCH) in Single Input Single Output (SISO), Multiple Input Single Output (MISO) and Multiple Input Multiple Output (MIMO) configurations. The data from higher layer are scrambled, modulated, layer mapped, precoded and mapped to resource elements in the transmitter. At the receiver, demapping from resource elements, decoding, delayer mapping, demodulation and descrambling have to be done by every physical channel. Simulation of these channels is carried out using ModelSim 6.4a and synthesis and implementation are done using PlanAhead 13.4 in Viretx-5 device. Implementation results include Register Transfer Level (RTL) design, power estimation, resource estimation and Field Programmable Gate Array (FPGA) editor.
Fpga Implementation of 3GPP-LTE Physical Downlink Control Channel Using Diversity Techniques
2013
Long Term Evolution (LTE) of UMTS Terrestrial Radio Access and Radio Access Network is a Fourth Generation wireless broadband technology which is capable of providing backward compatibility with 2G (Second Generation) and 3G (Third Generation) technologies. LTE is able to deliver high data rate and low latency with reduced cost This paper proposes a novel architecture for Single Input Single Output(SISO) 1x1, Multiple Input Single Output (MISO) 4x1, Multiple Input Multiple Output (MIMO)4x2 for Physical Downlink Control Channels of LTE. The physical downlink channel processing involves as scrambling, modulation, layer mapping, precoding, data mapping to resource elements at transmitter and demapping from resource elements, decoding, delayer mapping, demodulation and descrambling at receiver. In the proposed architecture, these steps are carried out in a single architecture comprises of all the data and control channels. Based on simulation and implementation, results are discussed in...
Fast Implementation of Different LTE Physical Downlink Control Channels Using FPGA
Springer , 2015
Hardware implementation of LTE-advanced systems using FPGA technology is a highly promising technology for mobile communications and wireless network researchers. The objective of this paper is to improve the processing speed; the system capabilities; the power consumption, and the processing delay of LTE-advanced downlink control channels due to the parallel processing nature of FPGA. Basically, the physical downlink control channel (PDCCH) is used to carry downlink control information (DCI). In which, an optimized HDL design for both transmitter and receiver of PDCCH will be presented. The design process of PDCCH transmitter and receiver are carried out in architecture under different antenna configurations including single input single output: multiple input multiple outputs (MIMO) 2 * 2, and MIMO 4* 4. The complete LTE-advanced physical layer has been coded using VHDL as one of the most famous HDL languages. Designs have been synthesized using Xilinx Integrated Software Environment tool 14.2 on Xilinx Virtex-5 XC5VLX220T_FF1738 as well as Xilinx Spartan-6 XC6SLX45_2CSG324, the performance indices of these two FPGA kits, will be compared. To simulate the system on ModelSim SE 6.5, based on synthesize and implementation, in terms of register transfer level design, FPGA editor, and Xilinx Power Analyzer are discussed into an FPGA kit from the Xilinx vendor. As a result of the system implementation process, it was found that speed; a number of registers and power consumption are improved. Finally, it is clear that the hardware is much faster than the software, as well as, reducing the power dissipation in Spartan-6 with respect to Vitex-5 FPGA configurations.
FPGA Implementation of LTE-Advanced Downlink Physical Layer Transceiver
2017
To achieve a higher bit rates up to 1 Gbps for meeting the growing needs of the users of the mobile communication system the 3rd Generation Partnership Project (3GPP) introduced the Long Term Evolution Advanced (LTE-A) as an advanced standard for the mobile communication systems. The new features added by the LTE-A on the physical layer is a direct consequence for applying new modulation and coding techniques for both the Uplink and Downlink. The Orthogonal Frequency Division Multiple Access (OFDMA) was applied for the Downlink and the Single Carrier Frequency Division Multiple Access (SC-FDMA) was applied for the Uplink as well as turbo coding. This paper presents the design and implementation of the LTE-A downlink transmitter and receiver using a Field Programmable Gate Array (FPGA) according to release 10/11 on Virtex 6 XC6VLX240T FPGA kit using Xilinx® ISE® Design Suite version 13.3.All stages of the LTE-A downlink physical layer (PYH) transceiver, besides the time and frequency...
Efficient Design and Implementation of LTE Downlink Control Information Decoder
International Journal of Computer Theory and Engineering, 2014
The decoding of Downlink Control Information (DCI) in LTE is based upon a process that is defined as a blind decoding which depends on a number of decoding attempts on a number of Physical Downlink Control Channel (PDCCH) candidate locations for a number of defined DCI formats. In this paper, two proposed designs for DCI decoder are presented. The first decodes based upon monitoring PDCCH candidate locations serially. This design can perform the whole 44 decoding attempts within 87.3 % of the whole OFDM symbol time with extended cyclic prefix. So, it's well suited for Multicast/Broadcast over Single Frequency Network (MBSFN) subframes. However, this design doesn't meet the worst-case time of an LTE OFDM symbol with normal cyclic prefix. Therefore, a second design is proposed that exploits parallelism to enable fast blind decoding process. The proposed parallel design proves efficiency in meeting decoding time constraints besides, consuming a little power with a proven efficiency in utilization area perspective. The proposed parallel design performs all of 44 decoding attempts in a time of 7.8 µs which is only 11.7 % of an LTE useful OFDM symbol time with a logic power consumption of only 17000 µW. The proposed designs are simulated using Modelsim 6.4a and implemented in Plan Ahead 14.4 in 28 nm technology, Virtex7 FPGA kit of part number XC7V2000T, which is characterized by high performance and large capacity.
VLSI Design, 2014
Physical control format indicator channel (PCFICH) carries the control information about the number of orthogonal frequency division multiplexing (OFDM) symbols used for transmission of control information in long term evolution-advanced (LTE-A) downlink system. In this paper, two novel low complexity receiver architectures are proposed to implement the maximum likelihood- (ML-) based algorithm which decodes the CFI value in field programmable gate array (FPGA) at user equipment (UE). The performance of the proposed architectures is analyzed in terms of the timing cycles, operational resource requirement, and resource complexity. In LTE-A, base station and UE have multiple antenna ports to provide transmit and receive diversities. The proposed architectures are implemented in Virtex-6 xc6vlx240tff1156-1 FPGA device for various antenna configurations at base station and UE. When multiple antenna ports are used at base station, transmit diversity is obtained by applying the concept of...
Realization of the SISO Architecture for PBCH of 3GPP-LTE using PlanAhead Tool and Virtex-5 Device
Journal of Wireless Networking and Communications, 2012
Wireless network has been improved after 3G by means of higher data rates with better coverage and by reducing latency. LTE is the technology that provides backward compatibility with 3G and 4G technologies. Compared with 3G, it offers high data rates of the order of 50Mbps for uplink and 100Mbps for downlink. LTE is able to provide services in scalable bandwidth (1.4, 3, 5, 10, 15 or 20 MHz). It uses the frame structure as Time Division Duplexing (TDD) and Frequency Division Duplexing (FDD). LTE technology uses different channels in both links for different applications. This paper mainly focuses on downlink channels, particularly data channels named as PDSCH, PBCH and PMCH. The main objective of this paper is the realization of the SISO (Single Input-Single Output) architecture of PBCH downlink data channel with its own transmitter and receiver. Information is processed at transmitter by means of scrambling, modulation, layer mapping, precoding and mapping to resource elements. Similar to the transmitter, receiver also has to perform some techniques to retrieve the original data such as demapping from resource elements, decoding, delayer mapping, demodulation and descrambling. Simulation of these steps for transmitter is done by using ModelSim 6.4a and the synthesis and implementation are done by using PlanAhead 13.2 virtex-5, xc5vlx50tff1136-1 board. Power estimation, resource estimation, RTL designs and FPGA editors are shown for the transmitter and receiver structure.