3-dimensional systolic architecture for parallel VLSI implementation of the discrete cosine transform (original) (raw)
1996, IEE Proceedings - Circuits, Devices and Systems
Two different linear systolic arrays have been suggested for the computation of discrcle cosine transform (DCT). The proposed linear arrays are compkmentary to each other in the sense that the o u q u t of the linear arrays of one type may be fed a s the input for the linear arrays of the other type. This feature of the proposed linear arrays has been utilised for designing a bilayer structure For computing thc prime-factor DCT. it is interesting to note that the proposed structure does noi. require any hardwarehime for transposition of the intermediate results. The desired transposit ion is achieved by orthogonal alignment of the linear arrays of the upper laycr with respect to .:hose of the lower layer. The proposed structures provide high throughput of computation due to fully pipelined processing, and massive parallelism employed in the bilayer architecturc.
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